Inventor

CHOUDHARY SWADESH

US33 patents

⚠️ This page may combine multiple inventors who share the name “CHOUDHARY SWADESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHOUDHARY SWADESH

INTEL CORP

Method and system for cache agent trace and capture

Parameter exchange for a die-to-die interconnect

Die-to-die interconnect

Encoder and decoder of forward error correction (FEC) codec

Method and system for cache agent trace and capture

Flexible on-die fabric interface

Streaming fabric interface

Standard interfaces for die to die (D2D) interconnect stacks

Compliance and debug testing of a die-to-die interconnect

Link layer-PHY interface adapter

On-package die-to-die (D2D) interconnect for memory using universal chiplet interconnect express (UCIe) PHY

Retimers to extend a die-to-die interconnect

Valid signal for latency sensitive die-to-die (D2D) interconnects

Clock-gating in die-to-die (D2D) interconnects

Encoder and decoder of forward error correction (FEC) codec

Forward error correction and cyclic redundancy check mechanisms for latency-critical coherency and memory interconnects

Link layer-PHY interface adapter

Shared resources for multiple communication traffics

Shared resources for multiple communication traffics

Integrated input/output management

Unified test and debug chiplet architecture

Selection of processing mode for receiver circuit

Flexible on-die fabric interface

Hardware logging for lane margining and characterization

System, apparatus and method for controlling traffic in a fabric

Logical physical layer interface specification support for PCie 6.0, cxl 3.0, and UPI 3.0 protocols

Lane repair and lane reversal implementation for die-to-die (D2D) interconnects

Link initialization training and bring up for die-to-die interconnect

Sideband interface for die-to-die interconnects

System, apparatus and method for handling multi-protocol traffic in data link layer circuitry

Performance level control in a data processing apparatus

Mission-critical computing architecture

INTEL CORPORAITON

System, apparatus and method for increasing bandwidth of edge-located agents of an integrated circuit