Inventor

KEELEY JAMES W

US35 patents

⚠️ This page may combine multiple inventors who share the name “KEELEY JAMES W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KEELEY JAMES W

BULL HN INFORMATION SYST

Recovery method and apparatus for a pipelined processing unit of a multiprocessor system

Cache resiliency in processing a variety of address faults

Multiprocessor system with centralized initialization, testing and monitoring of the system and providing centralized timing

Apparatus and method for providing more effective reiterations of interrupt requests in a multiprocessor system

Means for providing a graceful power shut-down capability in a multiprocessor system having certain processors not inherently having a power shut-down capability

Method and apparatus for avoiding processor deadly embrace in a multiprocessor system

Data processing system with a fast interrupt

Apparatus for loading and verifying a control store memory of a central subsystem

On-board diagnostic testing

Bus controller having state machine for translating commands and controlling accesses from system bus to synchronous bus having different bus protocols

Fast synchronization of asynchronous signals with a synchronous system

Programmable system bus priority network

Apparatus and method for providing more effective reiterations of processing task requests in a multiprocessor system

Processing unit having multiple synchronous bus for sharing access and regulating system bus access to synchronous bus

Processor bus access

Microprocessor bus interface protocol analyzer

Data processing system having a bus command generated by one subsystem on behalf of another subsystem

Method and apparatus for performing health tests of units of a data processing system

Power-on sequencing apparatus for initializing and testing a system processing unit

HONEYWELL INF SYSTEMS

Multiprocessor shared pipeline cache memory with split cycle and concurrent utilization

Shared interface apparatus for testing the memory sections of a cache unit

Multilevel cache system with graceful degradation capability

Test apparatus for testing a multilevel cache system with graceful degradation capability

Enable/disable control checking apparatus

Directory test error mode control apparatus

Channel number priority assignment apparatus

HONEYWELL BULL

Multiprocessor coherent cache system including two level shared cache with separately allocated processor storage locations and inter-level duplicate entry replacement

Resilient bus system

Resilient bus system

Read in process memory apparatus

Address transform method and apparatus for transferring addresses

Multiprocessor level change synchronization apparatus

BULL HN INFORAMTION SYSTEMS IN

Bus interface state machines with independent access to memory, processor and registers for concurrent processing of different types of requests

KEELEY JAMES W

Bridge apparatus and methods for coupling multiple non-fibre channel devices to a fibre channel arbitrated loop

LSI CORP

Apparatus and methods for access fairness for a multiple target bridge/router in a fibre channel arbitrated loop system