Inventor

WANG WEN-CHOU VINCENT

US44 patents

⚠️ This page may combine multiple inventors who share the name “WANG WEN-CHOU VINCENT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG WEN-CHOU VINCENT

FUJITSU LTD

Multi-layer opto-electronic substrates with electrical and optical interconnections and methods for making

Three-dimensional opto-electronic modules with electrical and optical interconnections and methods for making

Optical coupling structures and the fabrication processes

Opto-electronic substrates with electrical and optical interconnections and methods for making

Reduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like

Systems based on opto-electronic substrates with electrical and optical interconnections and methods for making

Reduced cross-talk noise high density signal interposer with power and ground wrap

Method of fabrication of multiple-layer high density substrate

Chip and board stress relief interposer

Controlled impedence interposer substrate

Electron-beam treatment procedure for patterned mask layers

Method for making a three-dimensional multichip module

Single and multilayer waveguides and fabrication process

Optical reflective structures and method for making

Device transfer method

Flip chip pre-assembly underfill process

Fabrication procedure for a stable post

Methods of planarizing structures on wafers and substrates by polishing

Controlled impedance interposer substrate and method of making

High density signal interposer with power and ground wrap

Methods of etching through wafers and substrates with a composite etch stop layer

Method of forming a pattern or via structure utilizing supplemental electron beam exposure and development to remove image residue

Method of fabricating a substrate with a via connection

Modules with pins and methods for making modules with pins

Methods of planarizing structures on wafers and substrates by polishing

High-yield methods of fabricating large substrate capacitors

Substrate with thin film capacitor and insulating plug

Multilayer circuit structure build up method

Methods of forming tall, high-aspect ratio vias and trenches in photo-imageable materials, photoresist materials, and the like

Multilayer interconnection and method

Pattern or via structure formed through supplemental electron beam exposure and development to remove image residue

Wet chemical processing techniques for plating high aspect ratio features

Structure and fabrication procedure for a stable post

Method of making a multichip module substrate

ALTERA CORP

Structure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrate

Pad surface finish for high routing density substrate of BGA packages

Flip chip package with warpage control

Integrated assembly-underfill flip chip process

Structure and material for assembling a low-K Si die to achieve a low warpage and industrial grade reliability flip chip package with organic substrate

Structure and material for assembling a low-K Si die to achieve a low warpage and industrial grade reliability flip chip package with organic substrate

Structure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrate

Structure, material, and design for assembling a low-K Si die to achieve an industrial grade reliability wire bonding package

(unassigned)

Multi-chip module and method for forming and method for deplating defective capacitors

WANG WEN-CHOU VINCENT

Structure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrate