Inventor
CHIU HSIEN-KUANG
TW18 patents
⚠️ This page may combine multiple inventors who share the name “CHIU HSIEN-KUANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG
10 patentsUS6265317B1Jul 24, 2001
Top corner rounding for shallow trench isolation
TAIWAN SEMICONDUCTOR MFG249 citations99
US6869868B2Mar 22, 2005
Method of fabricating a MOSFET device with metal containing gate structures
TAIWAN SEMICONDUCTOR MFG134 citations97
US6777299B1Aug 17, 2004
Method for removal of a spacer
TAIWAN SEMICONDUCTOR MFG17 citations92
US6703250B2Mar 9, 2004
Method of controlling plasma etch process
TAIWAN SEMICONDUCTOR MFG24 citations92
US6777340B1Aug 17, 2004
Method of etching a silicon containing layer using multilayer masks
TAIWAN SEMICONDUCTOR MFG17 citations82
US7037849B2May 2, 2006
Process for patterning high-k dielectric material
TAIWAN SEMICONDUCTOR MFG7 citations74
US6812044B2Nov 2, 2004
Advanced control for plasma process
TAIWAN SEMICONDUCTOR MFG7 citations74
US6828237B1Dec 7, 2004
Sidewall polymer deposition method for forming a patterned microelectronic layer
TAIWAN SEMICONDUCTOR MFG8 citations72
US7235153B2Jun 26, 2007
System for removal of a spacer
TAIWAN SEMICONDUCTOR MFG4 citations63
US7148114B2Dec 12, 2006
Process for patterning high-k dielectric material
TAIWAN SEMICONDUCTOR MFG2 citations63
ASUSTEK COMP INC
3 patentsWANG CHIH-HAO
2 patentsUS8097924B2Jan 17, 2012
Ultra-shallow junction MOSFET having a high-k gate dielectric and in-situ doped selective epitaxy source/drain extensions and a method of making same
WANG CHIH-HAO4 citations62
US8759185B2Jun 24, 2014
Ultra-shallow junction MOSFET having a high-k gate dielectric and in-situ doped selective epitaxy source/drain extensions and a method of making same
WANG CHIH-HAO0 citations51