Inventor
TELLEZ GUSTAVO ENRIQUE
US17 patents
Patents
17 patentsUS6247853B1Jun 19, 2001
Incremental method for critical area and critical region computation of via blocks
IBM100 citations95
US6993692B2Jan 31, 2006
Method, system and apparatus for aggregating failures across multiple memories and applying a common defect repair solution to all of the multiple memories
IBM25 citations92
US10223496B2Mar 5, 2019
Triple and quad coloring shape layouts
IBM7 citations83
US10747935B2Aug 18, 2020
Identification of hotspots in congestion analysis during physical design of integrated circuit
IBM3 citations73
US12423502B2Sep 23, 2025
Rule check heatmap prediction
IBM1 citations62
US12417333B2Sep 16, 2025
Short net pin alignment for routing
IBM0 citations62
US11983476B2May 14, 2024
Technology-independent line end routing
IBM1 citations62
US11829697B2Nov 28, 2023
Region-based layout routing
IBM0 citations62
US11734486B2Aug 22, 2023
Sweepline triangulation for spanning graphs
IBM0 citations62
US11087062B1Aug 10, 2021
Dynamic SADP region generation
IBM0 citations62
US10796064B2Oct 6, 2020
Autonomous placement to satisfy self-aligned double patterning constraints
IBM1 citations62
US12493730B2Dec 9, 2025
Timing-aware and simultaneous optimization of latch clustering and placement in an integrated circuit
IBM0 citations57
US11341311B1May 24, 2022
Generation and selection of universally routable via mesh specifications in an integrated circuit
IBM1 citations54
US10719656B2Jul 21, 2020
Triple and quad coloring of shape layouts
IBM0 citations51
US10606978B2Mar 31, 2020
Triple and quad coloring of shape layouts
IBM0 citations51
US11966682B2Apr 23, 2024
Fast independent checker for extreme ultraviolet (EUV) routing
IBM0 citations49
US11074379B2Jul 27, 2021
Multi-cycle latch tree synthesis
IBM0 citations49