Inventor

SANGHVI HETUL

US45 patents

⚠️ This page may combine multiple inventors who share the name “SANGHVI HETUL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SANGHVI HETUL

TEXAS INSTRUMENTS INC

Image processing accelerator

Scheduling of external block based data processing tasks on a hardware thread scheduler

Bandwidth controlled data synchronization for image and vision processor

Scheduling of concurrent block based data processing tasks on a hardware thread scheduler

Method for scheduling a processing device

Lossless data compression

Image processing accelerator

Method and apparatus for arbitrary output shape processing of an image

Three dimensional (3D) object detection

Debug for multi-threaded processing

Image processing accelerator

Scheduling of external block based data processing tasks on a hardware thread scheduler based on processing order

Three dimensional (3D) object detection

Method and apparatus for dynamic block partition of an image

Method and apparatus for arbitrary output shape processing of an image

Methods and apparatus to provide an efficient safety mechanism for signal processing hardware

Debug for multi-threaded processing

Bandwidth controlled data synchronization for image and vision processor

Data synchronization for image and vision processing blocks using pattern adapters

Methods and system for efficient processing of generic geometric correction engine

Three dimensional (3D) object detection

Down scaling images in a computer vision system

Methods and apparatus to provide an efficient safety mechanism for signal processing hardware

Debug for multi-threaded processing

Down scaling images in a computer vision system

Hierarchical data organization for dense optical flow processing in a computer vision system

Dense optical flow processing in a computer vision system

Dense optical flow processing in a computer vision system

Digital to analog conversion

Computation in-memory using 6-transistor bit cells

Dynamic frame padding in a video hardware engine

Three dimensional (3d) object detection

Method and apparatus for dynamic block partition of an image

Motion compensation with error, flag, reference, and decompressed reference data

Hierarchical data organization for dense optical flow processing in a computer vision system

System and method for an efficient hardware implementation of census transform

Dense optical flow processing in a computer vision system

System and method for an efficient hardware implementation of census transform

Dynamic frame padding in a video hardware engine

Processor instructions for accelerating video coding

Sparse optical flow support in an optical flow system

Performing cache bank operations in offset sequences from first bank

Low power ultra-HD video hardware engine

GUPTE AJIT DEEPAK

Lossy compression technique for video encoder bandwidth reduction using compression error data

Video compression searching reference frame in hybrid growing-window and sliding-window