Inventor
DAVIS MARK C
US38 patents
⚠️ This page may combine multiple inventors who share the name “DAVIS MARK C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
15 patentsUS9940130B2Apr 10, 2018
Rotate instructions that complete execution either without writing or reading flags
INTEL CORP4 citations84
US9940131B2Apr 10, 2018
Rotate instructions that complete execution either without writing or reading flags
INTEL CORP4 citations84
US9916160B2Mar 13, 2018
Rotate instructions that complete execution either without writing or reading flags
INTEL CORP4 citations84
US7243219B2Jul 10, 2007
Predicting instruction branches with a plurality of global predictors using varying amounts of history instruction
INTEL CORP18 citations83
US9164762B2Oct 20, 2015
Rotate instructions that complete execution without reading carry flag
INTEL CORP4 citations81
US8738893B2May 27, 2014
Add instructions to add three source operands
INTEL CORP5 citations81
US7533252B2May 12, 2009
Overriding a static prediction with a level-two predictor
INTEL CORP17 citations81
US11106461B2Aug 31, 2021
Rotate instructions that complete execution either without writing or reading flags
INTEL CORP2 citations73
US11900108B2Feb 13, 2024
Rotate instructions that complete execution either without writing or reading flags
INTEL CORP0 citations62
US12543594B2Feb 3, 2026
Scalable package architecture using reticle stitching and photonics for integrated circuits
INTEL CORP0 citations58
US12541476B2Feb 3, 2026
Chiplet architecture for late bind SKU fungibility
INTEL CORP0 citations52
US10649774B2May 12, 2020
Multiplication instruction for which execution completes without writing a carry flag
INTEL CORP0 citations52
US10152452B2Dec 11, 2018
Source operand read suppression for graphics processors
INTEL CORP0 citations52
US7562206B2Jul 14, 2009
Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions
INTEL CORP0 citations42
US7475225B2Jan 6, 2009
Method and apparatus for microarchitecture partitioning of execution clusters
INTEL CORP0 citations41
IBM
6 patentsUS6961849B1Nov 1, 2005
Selective data encryption using style sheet processing for decryption by a group clerk
IBM188 citations99
US6931532B1Aug 16, 2005
Selective data encryption using style sheet processing
IBM370 citations99
US7284147B2Oct 16, 2007
Reliable fault resolution in a cluster
IBM34 citations89
US8056123B2Nov 8, 2011
Method, apparatus and program storage device for providing service access control for a user interface
IBM9 citations79
US7281068B2Oct 9, 2007
Wireless-boot diskless mobile computing
IBM8 citations74
US7941690B2May 10, 2011
Reliable fault resolution in a cluster
IBM2 citations60
DAVIS MARK C
5 patentsUS9619282B2Apr 11, 2017
Task scheduling in big and little cores
DAVIS MARK C4 citations72
US8984200B2Mar 17, 2015
Task scheduling in big and little cores
DAVIS MARK C5 citations72
US8131986B2Mar 6, 2012
System and method for boot loading of programs within a host operating environment having one or more linked guest operating systems
DAVIS MARK C2 citations62
US8566489B2Oct 22, 2013
Systems and methods for sharing a wireless antenna in a hybrid environment
DAVIS MARK C4 citations60
US9507558B2Nov 29, 2016
Systems and methods for shared display in a hybrid environment
DAVIS MARK C0 citations29
GOPAL VINODH
3 patentsUS8549264B2Oct 1, 2013
Add instructions to add three source operands
GOPAL VINODH6 citations84
US8504807B2Aug 6, 2013
Rotate instructions that complete execution without reading carry flag
GOPAL VINODH4 citations74
US9990201B2Jun 5, 2018
Multiplication instruction for which execution completes without writing a carry flag
GOPAL VINODH1 citations51