Inventor

PELELLA ANTONIO R

US23 patents

⚠️ This page may combine multiple inventors who share the name “PELELLA ANTONIO R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PELELLA ANTONIO R

IBM

Fast edge triggered self-resetting CMOS receiver with parallel L1/L2 (master/slave) latch

Local bit select with suppression of fast read before write

Local bit select circuit with slow read recovery scheme

Coupled body contacts for SOI differential circuits

Fast edge triggered self-resetting CMOS receiver with parallel L1/L2 (Master/Slave) latch

High performance dual-stage sense amplifier circuit

Global bit select circuit with dual read and write bit line pairs

Method of converting short duration input pulses to longer duration output pulses

Self-resetting CMOS multiplexer with static output driver

Global bit select circuit interface with dual read and write bit line pairs

Split L2 latch with glitch free programmable delay

Global bit line restore timing scheme and circuit

Global bit line restore timing scheme and circuit

Two stage SRCMOS sense amplifier

Sense and hold amplifier

Cache late select circuit

High performance pseudo dynamic pulse controllable multiplexer

Self timed pre-charged address compare logic circuit

Method of resetting a CMOS amplifier

Output driver with pulse to static converter

PELELLA ANTONIO R

Global bit select circuit with write around capability

CHAN YUEN H

Single clock dynamic compare circuit

JOSHI RAJIV V

Robust local bit select circuitry to overcome timing mismatch