Inventor
TUMINARO ARTHUR D
US9 patents
Patents
9 patentsUS7113433B2Sep 26, 2006
Local bit select with suppression of fast read before write
IBM23 citations92
US7336546B2Feb 26, 2008
Global bit select circuit with dual read and write bit line pairs
IBM11 citations83
US7463537B2Dec 9, 2008
Global bit select circuit interface with dual read and write bit line pairs
IBM7 citations73
US7006403B2Feb 28, 2006
Self timed bit and read/write pulse stretchers
IBM8 citations73
US7272030B2Sep 18, 2007
Global bit line restore timing scheme and circuit
IBM8 citations72
US7170774B2Jan 30, 2007
Global bit line restore timing scheme and circuit
IBM9 citations72
US5627484AMay 6, 1997
CMOS sense amplifier
IBM11 citations72
US5239506AAug 24, 1993
Latch and data out driver for memory arrays
IBM10 citations69
US6958943B1Oct 25, 2005
Programmable sense amplifier timing generator
IBM5 citations60