Inventor

SRINIVAS MYSORE SATHYANARAYANA

US32 patents

⚠️ This page may combine multiple inventors who share the name “SRINIVAS MYSORE SATHYANARAYANA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SRINIVAS MYSORE SATHYANARAYANA

IBM

Apparatus and method for initial load balancing in a multiple run queue system

Method and apparatus for managing access contention to a linear list without the use of locks

Scheduling threads in a multiprocessor computer

System and method for scheduling compatible threads in a simultaneous multi-threading processor using cycle per instruction value occurred during identified time interval

Dynamic memory management of unallocated memory in a logical partitioned data processing system

System and method for dynamically adjusting read ahead values based upon memory usage

System and method for thread scheduling with weak preemption policy

Scheduling threads in a multiprocessor computer

Scheduling compatible threads in a simultaneous multi-threading processor using cycle per instruction value occurred during identified time interval

Efficient memory update process for on-the-fly instruction translation for well behaved applications executing on a weakly-ordered processor

System and method for CPI load balancing in SMT processors

Measuring processor use in a hardware multithreading processor environment

System and method for dynamically adjusting read ahead values based upon memory usage

Method and system for using upper cache history information to improve lower cache data replacement

System and method for CPI load balancing in SMT processors

Using a plurality of tables for improving performance in predicting branches in processor instructions

Bus access moderation system

ANAND VAIJAYANTHIMALA K

Optimizing system performance using spare cores in a virtualized environment

Extending cache capacity on multiple-core processor systems

Partition redispatching using page tracking

FLEMMING DIANE GARZA

Managing thermal condition of a memory

Two partition accelerator and application of tiered flash to cache hierarchy in partition acceleration

Flexible use of extended cache using a partition cache footprint

MEWHINNEY GREG R

Optimized least recently used lookup cache

Standalone software performance optimizer system for hybrid systems

ACCAPADI MATTHEW

Managing migration of a prefetch stream from one processor core to another processor core

Managing migration of a prefetch stream from one processor core to another processor core

OLSZEWSKI BRET RONALD

Measuring processor use in a hardware multithreading processor environment

CHEN WEN-TZER THOMAS

Method and apparatus for instruction completion stall identification in an information handling system

DUNSHEA ANDREW

Efficient memory update process for well behaved applications executing on a weakly-ordered processor

CHIANG MEN-CHOW

System and method for enabling micro-partitioning in a multi-threaded processor

BELL JR ROBERT H

Partial line cache write injector for direct memory access write