Inventor

PELLEY III PERRY H

US45 patents

⚠️ This page may combine multiple inventors who share the name “PELLEY III PERRY H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PELLEY III PERRY H

MOTOROLA INC

Voltage regulator for regulating an output voltage from a charge pump and method therefor

Static random access memory resistant to soft error

Trench cell for a dram

Localized ATD summation for a memory

Memory with redundancy and predecoded signals

Technique restore for a dynamic random access memory

Sense amplifier

Address comparison in an inteagrated circuit memory having shared read global data lines

Integrated circuit memory with column redundancy having shared read global data lines

ECL to CMOS translator

RAM with dual precharge circuit and write recovery circuitry

Output buffer with improved di/dt

Precharge of a dram data line to an intermediate voltage

Address buffer circuit for a dram

BICMOS latch circuit for latching differential signals

Charge pump having reduced threshold voltage losses

Address buffer with ATD generation

Output buffer and method therefor

Output buffer

BICMOS level converter circuit

Power supply dependent input buffer

Memory using distributed data line loading

Redundant column substitution architecture with improved column access time

TTL to ECL input buffer

Using delay to obtain high speed current driver circuit

FREESCALE SEMICONDUCTOR INC

Inductive device including bond wires

Multiple core system

Dynamic random access memory (DRAM) refresh

Groups of serially coupled processor cores propagating memory write packet while maintaining coherency within each group towards a switch coupled to memory partitions

Memory with level shifting word line driver and method thereof

Memory device with sense amplifier and self-timed latch

Double-rate memory

Integrated circuit with a transitor over an interconnect layer

Memory having sense time of variable duration

Power supply selection for multiple circuits on an integrated circuit

Memory with level shifting word line driver and method thereof

Embedded substrate interconnect for underside contact to source and drain regions

Memory with clocked sense amplifier

Embedded substrate interconnect for underside contact to source and drain regions

PELLEY III PERRY H

Dynamic random access memory (DRAM) refresh

Coherency groups of serially coupled processing cores propagating coherency information containing write packet to memory

Memory system with error correction and method of operation

INTEL CORP

Byte-wide dynamic RAM with multiplexed internal buses

MOLOROLA INC

Low di/dt BiCMOS output buffer with improved speed

PESSOA LUCIO F C

Testing of multiple integrated circuits