Inventor

CHOQUETTE JACK H

US36 patents

⚠️ This page may combine multiple inventors who share the name “CHOQUETTE JACK H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHOQUETTE JACK H

NVIDIA CORP

Generalized acceleration of matrix multiply accumulate operations

Generalized acceleration of matrix multiply accumulate operations

System and processor that include an implementation of decoupled pipelines

Persistent scratchpad memory for data exchange between programs

Generalized acceleration of matrix multiply accumulate operations

System, method, and computer program product for implementing software-based scoreboarding

Execution of divergent threads using a convergence barrier

System, method, and computer program product for implementing multi-cycle register file bypass

Generalized acceleration of matrix multiply accumulate operations

Generalized acceleration of matrix multiply accumulate operations

Generalized acceleration of matrix multiply accumulate operations

Generalized acceleration of matrix multiply accumulate operations

Generalized acceleration of matrix multiply accumulate operations

Decompression techniques for processing compressed data suitable for artificial neural networks

Application programming interface to provide information

Application programming interface to wait on matrix multiply-accumulate

System, method, and computer program product for managing out-of-order execution of program instructions

Memory management using a register

System and processor for implementing interruptible batches of instructions

AZUL SYSTEMS INC

Write-back cache with different ECC codings for clean and dirty lines with refetching of uncorrectable clean lines

Speculative multiaddress atomicity

Multi-level power monitoring, filtering and throttling at local blocks and globally

Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor system

Detecting software race conditions

Array access

Cooperative preemption

SANDCRAFT INC

Floating-point and integer multiply-add and multiply-accumulate

Circuit, architecture and method for analyzing the operation of a digital processing system

Method and apparatus for vector register with scalar values

Processor with multiple execution units and local and global register bypasses

Method and apparatus for communicating signals between circuits operating at different frequencies

System bus arbitrator for facilitating multiple transactions in a computer system

CHOQUETTE JACK H

Pipelined processing with commit speculation staging buffer and load/store centric exception handling

Processor instruction used to perform a matrix test to generate a memory-related trap

TENE GIL

Cooperative preemption

GROVE DANIEL DWIGHT

Detecting software race conditions