Inventor

BORKENHAGEN JOHN M

US40 patents

⚠️ This page may combine multiple inventors who share the name “BORKENHAGEN JOHN M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BORKENHAGEN JOHN M

IBM

Background completion of instruction and associated fetch request in a multithread processor

Multi-level memory architecture with data prioritization

System and method for automatically configuring translation of logical addresses to a physical memory address in a computer memory system

Structure for selecting processors for job scheduling using measured power consumption

Structure for hub for supporting high capacity memory subsystem

Memory compression implementation in a multi-node server system with directly attached processor memory

Dynamic latency map for memory optimization

Efficient memory usage in systems including volatile and high-density memories

Reducing impact of a switch failure in a switch fabric via switch cards

Switch fabric management

Method and apparatus for detecting oscillator stuck faults in a level sensitive scan design (LSSD) system

Reducing impact of a repair action in a switch fabric

Memory compression implementation using non-volatile memory in a multi-node server system with directly attached processor memory

Structure for memory chip for high capacity memory subsystem supporting multiple speed bus

Memory compression implementation in a system with directly attached processor memory

Associativity implementation in a system with directly attached processor memory

Structure and method of implementing power savings during addressing of DRAM architectures

Reducing impact of repair actions following a switch failure in a switch fabric

Read prediction algorithm to provide low latency reads with SDRAM cache

Structure for memory chip for high capacity memory subsystem supporting replication of command data

Design structure of implementing power savings during addressing of DRAM architectures

Production of limited lifetime devices achieved through E-fuses

Methods and apparatus for using memory

Structure for dual-mode memory chip for high capacity memory subsystem

Spider web interconnect topology utilizing multiple port connection

ARMSTRONG WILLIAM J

Switch fabric management

Reducing impact of repair actions following a switch failure in a switch fabric

Reducing impact of a repair action in a switch fabric

Reducing impact of a switch failure in a switch fabric via switch cards

LENOVO ENTPR SOLUTIONS SINGAPORE PTE LTD

Applying firmware updates in a system with zero downtime by selectively offlining and onlining hardware using a scale-up hypervisor layer

Mirroring high performance and high availablity applications across server computers

Dynamic formation of symmetric multi-processor (SMP) domains

Repairing a hardware component of a computing system while workload continues to execute on the computing system

BARTLEY GERALD K

Sorting movable memory hierarchies in a computer system

Structure for multi-level memory architecture with data prioritization

Implementing memory interface with configurable bandwidth

ABALI BULENT

Managing shared computer memory using multiple interrupts

DAY II MICHAEL D

Virtual machine data structures corresponding to nested virtualization levels

GLOBALFOUNDRIES INC

Optimal positioning of reflecting optical devices

BORKENHAGEN JOHN M

Memory mirroring with memory compression