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Inventor

TRICKETT DOUGLAS M

US16 patents
⚠️ This page may combine multiple inventors who share the name “TRICKETT DOUGLAS M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

10 patents
US9373582B1Jun 21, 2016

Self aligned via in integrated circuit

IBM18 citations92
US9613862B2Apr 4, 2017

Chamferless via structures

IBM14 citations91
US9385078B1Jul 5, 2016

Self aligned via in integrated circuit

IBM11 citations83
US10032668B2Jul 24, 2018

Chamferless via structures

IBM4 citations82
US9252051B1Feb 2, 2016

Method for top oxide rounding with protection of patterned features

IBM3 citations73
US10388565B2Aug 20, 2019

Chamferless via structures

IBM1 citations71
US9768113B2Sep 19, 2017

Self aligned via in integrated circuit

IBM1 citations62
US10957588B2Mar 23, 2021

Chamferless via structures

IBM0 citations61
US10937694B2Mar 2, 2021

Chamferless via structures

IBM0 citations61
US10903118B2Jan 26, 2021

Chamferless via structures

IBM0 citations61

GLOBALFOUNDRIES INC

2 patents
US9373543B1Jun 21, 2016

Forming interconnect features with reduced sidewall tapering

GLOBALFOUNDRIES INC19 citations80
US9799559B1Oct 24, 2017

Methods employing sacrificial barrier layer for protection of vias during trench formation

GLOBALFOUNDRIES INC2 citations69

HITACHI HIGH TECH CORP

1 patent
US6875477B2Apr 5, 2005

Method for coating internal surface of plasma processing chamber

HITACHI HIGH TECH CORP411 citations98

TRICKETT DOUGLAS M

1 patent
US8476165B2Jul 2, 2013

Method for thinning a bonding wafer

TRICKETT DOUGLAS M223 citations97

TOKYO ELECTRON LTD

1 patent
US7279427B2Oct 9, 2007

Damage-free ashing process and system for post low-k etch

TOKYO ELECTRON LTD18 citations83

FEURPRIER YANNICK

1 patent
US8202803B2Jun 19, 2012

Method to remove capping layer of insulation dielectric in interconnect structures

FEURPRIER YANNICK7 citations81