Inventor

NARUI SEIJI

JP53 patents

⚠️ This page may combine multiple inventors who share the name “NARUI SEIJI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NARUI SEIJI

MICRON TECHNOLOGY INC

Memory core chip having TSVS

Semiconductor device including spiral data path

High bandwidth memory having plural channels

Stack access control for memory device

System and method for write data bus control in a stacked memory device

Semiconductor device with first-in-first-out circuit

Apparatuses, systems, and methods for read clock timing alignment in stacked memory devices

Methods and apparatuses for aligning read data in a stacked semiconductor device

Memory core chip having TSVs

Methods and apparatuses for aligning read data in a stacked semiconductor device

Memory device with write data bus control

High bandwidth memory having plural channels

Semiconductor device with first-in-first-out circuit

Semiconductor layered device with data bus inversion

Semiconductor layered device with data bus inversion

Apparatuses, systems, and methods for counter-based read clock in stacked memory devices

Apparatuses and methods for semiconductor devices including clock signal lines

Apparatuses and methods for semiconductor devices including clock signal lines

Stack access control for memory device

Memory device with write data bus control

HITACHI LTD

Semiconductor integrated circuit device and method for manufacturing the same

Semiconductor integrated circuit device and method for production of the same

Dynamic RAM, semiconductor storage device, and semiconductor integrated circuit device

Boosted potential generation circuit and control method

Semiconductor integrated circuit device and method for manufacturing the same

Semiconductor device

Dynamic memory

Dynamic random access memory (RAM), semiconductor storage device, and semiconductor integrated circuit (IC) device

Semiconductor integrated circuit device including memory cell section having capacitor over bitline structure and with the memory and peripheral sections having contact plug structures containing a barrier film and effecting electrical contact with misfets of both memory and peripheral sections

Semiconductor memory including a circuit for selecting redundant memory cells

NARUI SEIJI

Semiconductor device that performs refresh operation

Semiconductor device having charge pump circuit and information processing apparatus including the same

Semiconductor device that performs refresh operation

Semiconductor device having hierarchically structured bit lines and system including the same

Semiconductor device having hierarchically structured bit lines and system including the same

Semiconductor device having hierarchically structured bit lines and system including the same

ELPIDA MEMORY INC

Semiconductor device having hierarchically structured bit lines and system including the same

Semiconductor device having hierarchically structured bit lines and system including the same

Semiconductor device

Fine pitch grid array type semiconductor device

Semiconductor device having hierarchically structured bit lines and system including the same

Layout method for miniaturized memory array area

PS4 LUXCO SARL

Semiconductor storage device and system provided with same

Semiconductor device having ODT function

Semiconductor device, method for controlling the same, and semiconductor system

Semiconductor device having a complementary field effect transistor

Semiconductor device, method for controlling the same, and semiconductor system

MIYATAKE SHINICHI

Semiconductor device that can adjust substrate voltage

Semiconductor device having a complementary field effect transistor

FURUTANI KIYOHIRO

Semiconductor device, method for controlling the same, and semiconductor system