Inventor

CHENCINSKI EDWARD W

US15 patents

⚠️ This page may combine multiple inventors who share the name “CHENCINSKI EDWARD W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

11 patents

US5590309ADec 31, 1996

Storage protection cache and backing storage having system control element data cache pipeline and storage protection bits in a stack array with a stack directory for the stack array

IBM45 citations87

US10552054B2Feb 4, 2020

Peripheral component interconnect express (PCIE) network with input/output (I/O) chaining to reduce communication time within execution of I/O channel operations

IBM2 citations72

US6963977B2Nov 8, 2005

Peripheral component interconnect express (PCIE) network with input/output (I/O) operation chaining to reduce communication time within execution of I/O channel operations

IBM0 citations62

US11379390B1Jul 5, 2022

In-line data packet transformations

IBM0 citations51

US9423804B2Aug 23, 2016

Control of solid state memory device temperature using queue depth management

IBM0 citations49

US11681567B2Jun 20, 2023

Method and processor system for executing a TELT instruction to access a data item during execution of an atomic primitive

IBM0 citations48

US11321146B2May 3, 2022

Executing an atomic primitive in a multi-core processor system

IBM0 citations48

CHENCINSKI EDWARD W

4 patents

US8582778B2Nov 12, 2013

Integrated key server

CHENCINSKI EDWARD W0 citations49

US8880957B2Nov 4, 2014

Facilitating processing in a communications environment using stop signaling

CHENCINSKI EDWARD W1 citations48

US8880956B2Nov 4, 2014

Facilitating processing in a communications environment using stop signaling

CHENCINSKI EDWARD W0 citations48

US8787155B2Jul 22, 2014

Sideband error signaling

CHENCINSKI EDWARD W1 citations48

CHENCINSKI EDWARD W

IBM

Storage protection cache and backing storage having system control element data cache pipeline and storage protection bits in a stack array with a stack directory for the stack array

Peripheral component interconnect express (PCIE) network with input/output (I/O) chaining to reduce communication time within execution of I/O channel operations

Circuits and methods for modular exponentiation

Control of solid state memory device temperature using queue depth management

Control of solid state memory device temperature using queue depth management

Sideband error signaling

Peripheral component interconnect express (PCIE) network with input/output (I/O) operation chaining to reduce communication time within execution of I/O channel operations

In-line data packet transformations

Control of solid state memory device temperature using queue depth management

Method and processor system for executing a TELT instruction to access a data item during execution of an atomic primitive

Executing an atomic primitive in a multi-core processor system

CHENCINSKI EDWARD W

Integrated key server

Facilitating processing in a communications environment using stop signaling

Facilitating processing in a communications environment using stop signaling

Sideband error signaling