Inventor

PAN PHILIP

US51 patents

⚠️ This page may combine multiple inventors who share the name “PAN PHILIP”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAN PHILIP

ALTERA CORP

Programmable logic integrated circuit devices with differential signaling capabilities

Programmable high speed I/O interface

On/off reference voltage switch for multiple I/O standards

Programmable high speed I/O interface

Input buffer for multiple differential I/O standards

Control circuit for self-compensating delay chain for multiple-data-rate interfaces

High-performance memory interface circuit architecture

Self-compensating delay chain for multiple-date-rate interfaces

Multiple data rate interface architecture

Loop circuitry with low-pass noise filter

Multiple data rate interface architecture

Schmitt trigger circuit with adjustable trip point voltages

Multiple data rate interface architecture

Input buffer for multiple differential I/O standards

Input buffer for multiple differential I/O standards

Parallel programming of programmable logic using register chains

Supply voltage detection circuit

Programmable high speed interface

Apparatus and method for the arithmetic over-ride of look up table outputs in a programmable logic device

Distributed memory in field-programmable gate array integrated circuit devices

Implementation of double data rate embedded memory in programmable devices

Distributed memory in field-programmable gate array integrated circuit devices

Loop circuitry with low-pass noise filter

Multiple data rate interface architecture

Look-up table based memory

Programmable, staged, bus hold and weak pull-up for bi-directional I/O

Hi-speed parallel configuration of programmable logic

Supply voltage detection circuit

Techniques for implementing address recycling in memory circuits

Supply voltage detection circuit

Programmable high-speed interface

Method and apparatus to minimize clock tree skew in ICs

High-performance memory interface circuit architecture

Multiple data rate interface architecture

Self-compensating delay chain for multiple-date-rate interfaces

Multiple data rate interface architecture

Apparatus and methods for providing redundancy in integrated circuits

Scaleable look-up table based memory

Scaleable look-up table based memory

Address control for efficient memory partition

Techniques for preloading data into memory on programmable circuits

High-performance memory interface circuit architecture

Memory circuitry with data validation

PAN PHILIP

Multiple data rate interface architecture

Multiple data rate interface architecture

Scaleable look-up table based memory

Scaleable look-up table based memory

HUANG JOSEPH

High performance memory interface circuit architecture

High-performance memory interface circuit architecture

WANG BONNIE I

Programmable high-speed interface