Inventor

KASSAB MARK

US43 patents

⚠️ This page may combine multiple inventors who share the name “KASSAB MARK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KASSAB MARK

MENTOR GRAPHICS CORP

Test pattern compression for an integrated circuit test environment

Continuous application and decompression of test patterns to a circuit-under-test

Decompressor/PRPG for applying pseudo-random and deterministic test patterns

Method and apparatus for selectively compacting test responses

Low power scan testing techniques and apparatus

Multi-stage test response compactors

Timing-aware test generation and fault simulation

Timing-aware test generation and fault simulation

Generating responses to patterns stimulating an electronic circuit with timing exception paths

Method for synthesizing linear finite state machines

Timing-aware test generation and fault simulation

Continuous application and decompression of test patterns and selective compaction of test responses

Multi-stage test response compactors

Continuous application and decompression of test patterns and selective compaction of test responses

Continuous application and decompression of test patterns and selective compaction of test responses

RAJSKI JANUSZ

Test pattern compression for an integrated circuit test environment

Decompressor/PRPG for applying pseudo-random and deterministic test patterns

Multi-stage test response compactors

Method and apparatus for selectively compacting test responses

Test pattern compression for an integrated circuit test environment

Decompressor/PRPG for applying pseudo-random and deterministic test patterns

Continuous application and decompression of test patterns to a circuit-under-test

Method for synthesizing linear finite state machines

Method and apparatus for selectively compacting test responses

Continuous application and decompression of test patterns and selective compaction of test responses

(unassigned)

Method and apparatus for selectively compacting test responses

Decompressor/PRPG for applying pseudo-random and deterministic test patterns

Method and apparatus for selectively compacting test responses

Test pattern compression for an integrated circuit test environment

Method for synthesizing linear finite state machines

Test pattern compression for an integrated circuit test environment

Method for synthesizing linear finite state machines

Method for synthesizing linear finite state machines

LIN XIJIANG

Low power scan testing techniques and apparatus

Timing-aware test generation and fault simulation

Timing-aware test generation and fault simulation

UDELL JON

Methods for distributing programs for generating test data

Methods for distributing programs for generating test data

Methods for distribution of test generation programs

GOSWAMI DHIRAJ

Generating responses to patterns stimulating an electronic circuit with timing exception paths

RAJSKI JANSUZ

Continuous application and decompression of test patterns to a circuit-under-test

NORTHERN TELECOM LTD

Self-testable digital integrator

KASSAB MARK

Test scheduling and test access in test compression environment