Inventor

LIU RU-GUN

TW382 patents

⚠️ This page may combine multiple inventors who share the name “LIU RU-GUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIU RU-GUN

TAIWAN SEMICONDUCTOR MFG

Spacer etching process for integrated circuit design

Method and system of mask data preparation for curvilinear mask patterns for a device

Apparatus and method for immersion lithography

Methodology of optical proximity correction optimization

Method for integrated circuit mask patterning

Removal of line end shortening in microlithography and mask set for removal

Contour alignment system

Lithography using high selectivity spacers for pitch reduction

Method of merging color sets of layout

Self-alignment for using two or more layers and methods of forming same

Method for integrated circuit patterning

Mask error enhancement factor (MEEF) aware mask rule check (MRC)

Electron beam data storage system and method for high volume manufacturing

Table-based DFM for accurate post-layout analysis

Model import for electronic design automation

Electrical parameter extraction for integrated circuit design

Method for detection and scoring of hot spots in a design layout

Dissection splitting with optical proximity correction and mask rule check enforcement

TAIWAN SEMICONDUCTOR MFG CO LTD

Method of spacer patterning to form a target integrated circuit pattern

Via-free interconnect structure with self-aligned metal line interconnections

Method for validating measurement data

System and method for pattern correction in e-beam lithography

Lithography using high selectivity spacers for pitch reduction

Environmental-surrounding-aware OPC

Method of forming semiconductor device including source/drain contact having height below gate stack

Method of fabricating semiconductor device with reduced trench distortions

Optical proximity correction and photomasks

Method of manufacturing semiconductor devices

Buried metal track and methods forming same

Mask process correction

Pattern fidelity enhancement

Method of manufacturing semiconductor devices

Metal rail conductors for non-planar semiconductor devices

WANG HUNG-CHUN

Pattern correction with location effect

Methodology of optical proximity correction optimization

Geometric pattern data quality verification for maskless lithography

Striping methodology for maskless lithography

Method for high volume e-beam lithography

Providing electron beam proximity effect correction by simulating write operations of polygonal shapes

Electron beam data storage system and method for high volume manufacturing

CHEN HUANG-YU

Cell layout for multiple patterning technology

Method and apparatus for achieving multiple patterning technology compliant design layout

CHANG CHING-HSU

Extreme ultraviolet light (EUV) photomasks, and fabrication methods thereof

LIU RU-GUN

Method for making a mask by forming a phase bar in an integrated circuit design layout

CHENG YI-KAN

Routing method for double patterning design

CHIANG CHIA-PING

Dissection splitting with optical proximity correction to reduce corner rounding

TSAI CHENG-LUNG

Pattern recognition for integrated circuit design

CHENG NIAN-FUH

Fracture aware OPC

OU TSONG-HUA

Adaptive fin design for FinFETs

CHEN PI-TSUNG

Decomposing integrated circuit layout