Inventor

TSAI TSUNG-CHIEH

TW36 patents

⚠️ This page may combine multiple inventors who share the name “TSAI TSUNG-CHIEH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TSAI TSUNG-CHIEH

TAIWAN SEMICONDUCTOR MFG CO LTD

Different scaling ratio in FEOL/ MOL/ BEOL

Cell layout and structure

Different scaling ratio in FEOL / MOL/ BEOL

Method, system and software for accessing design rules and library of design features while designing semiconductor device layout

Different scaling ratio in FEOL / MOL/ BEOL

Semiconductor device having a metal gate

Different scaling ratio in FEOL / MOL/ BEOL

Gate-all-around device with different channel semiconductor materials and method of forming the same

Gate-all-around device with different channel semiconductor materials and method of forming the same

Cell layout and structure

Conductive line patterning

Checkerboard dummy design for epitaxial open ratio

Semiconductor structure and method for manufacturing thereof

Mask optimization for multi-layer contacts

Conductive line patterning

Semiconductor device, layout of semiconductor device, and method of manufacturing semiconductor device

Conductive line patterning

Semiconductor device and fabrication method thereof

Cell layout and structure

Method for preventing photoresist corner rounding effects

Implant region definition

Semiconductor structure and forming method thereof

Semiconductor device and manufacturing method thereof

TAIWAN SEMICONDUCTOR MFG

Conductive line patterning

Method for forming a high quality chemical oxide on a freshly cleaned silicon surface as a native oxide replacement

Semiconductor device and fabrication method thereof

Semiconductor wafer support

Apparatus and method for reducing solvent residue in a solvent-type dryer for semiconductor wafers

Mask optimization for multi-layer contacts

Implant region definition

Semiconductor device and fabrication method therefor

Electrostatic charge-free solvent-type dryer for semiconductor wafers

TSAI TSUNG-CHIEH

Semiconductor device fabrication method

YEH MING-HSI

Semiconductor device having a treated gate structure and fabrication method thereof

CHEN CHIN-AN

Method, system and software for accessing design rules and library of design features while designing semiconductor device layout

CHUANG HARRY-HAK-LAY

Controlling gate formation for high density cell layout