Inventor

WU JUING-YI

TW23 patents

⚠️ This page may combine multiple inventors who share the name “WU JUING-YI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WU JUING-YI

TAIWAN SEMICONDUCTOR MFG CO LTD

Different scaling ratio in FEOL/ MOL/ BEOL

Cell layout and structure

Different scaling ratio in FEOL / MOL/ BEOL

Method, system and software for accessing design rules and library of design features while designing semiconductor device layout

Different scaling ratio in FEOL / MOL/ BEOL

Semiconductor device having a metal gate

Different scaling ratio in FEOL / MOL/ BEOL

Cell layout and structure

Conductive line patterning

Mask optimization for multi-layer contacts

Conductive line patterning

Conductive line patterning

Cell layout and structure

Method for preventing photoresist corner rounding effects

Implant region definition

Semiconductor device and manufacturing method thereof

TAIWAN SEMICONDUCTOR MFG

Conductive line patterning

Mask optimization for multi-layer contacts

Implant region definition

Partially photoexposed positive photoresist layer blocking method for regio-selectively processing a microelectronic layer

TAIWAN SEMICONDUCTOR MANFACTUR

LOCOS field oxide and field oxide process using silicon nitride spacers

TAIWAN SEMICONDUCTOR MANUAFACT

Electrostatic discharge protector for an integrated circuit

CHEN CHIN-AN

Method, system and software for accessing design rules and library of design features while designing semiconductor device layout