Inventor

BALAKRISHNAN KEDARNATH

IN48 patents

⚠️ This page may combine multiple inventors who share the name “BALAKRISHNAN KEDARNATH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BALAKRISHNAN KEDARNATH

ADVANCED MICRO DEVICES INC

Fine granularity refresh

Scheduling memory requests with non-uniform latencies

Memory controller with flexible address decoding

Configuring dynamic random access memory refreshes for systems having multiple ranks of memory

Memory controller arbiter with streak and read/write transaction management

Supporting responses for memory types with non-uniform latencies on same channel

Data integrity for persistent memory systems and the like

Command replay for non-volatile dual inline memory modules

Low power memory throttling

Memory controller with virtual controller mode

Refresh management for DRAM

Dynamic page state aware scheduling of read/write burst transactions

Dynamic per-bank and all-bank refresh

Command arbitration for high speed memory interfaces

Credit scheme for multi-queue memory controllers

Directed refresh management for DRAM

Refresh during power state changes

Staging memory access requests

Memory calibration system and method

Full dynamic post-package repair

Channel and sub-channel throttling for memory controllers

Error recovery for non-volatile memory modules

Performance of bank refresh

Error reporting for non-volatile memory modules

Signalling for heterogeneous memory systems

Data integrity for persistent memory systems and the like

Refresh management for memory

Write bank group mask during arbitration

Memory calibration system and method

Error recovery for non-volatile memory modules

Error reporting for non-volatile memory modules

Speculative exit from power down mode of a dynamic random access memory rank

Signaling for heterogeneous memory systems

Dynamic page state aware scheduling of read/write burst transactions

Scheduling memory requests with non-uniform latencies

Supporting responses for memory types with non-uniform latencies on same channel

Memory controller with a plurality of command sub-queues and corresponding arbiters

Memory controller with a plurality of command sub-queues and corresponding arbiters

Memory encryption

Refresh management for DRAM

Fine granularity refresh

Memory controller with hybrid DRAM/persistent memory channel arbitration

Adaptive page close prediction

DDR memory error recovery

NEC LAB AMERICA INC

Method for generating, from a test cube set, a generator configured to generate a test pattern

Method and apparatus for testing logic circuit designs

Method and apparatus for testing logic circuit designs

Test pattern compression with pattern-independent design-independent seed compression