Inventor

HSIEH KEN-HSIEN

TW103 patents

⚠️ This page may combine multiple inventors who share the name “HSIEH KEN-HSIEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HSIEH KEN-HSIEN

TAIWAN SEMICONDUCTOR MFG CO LTD

Via-free interconnect structure with self-aligned metal line interconnections

Multi-patterning conflict free integrated circuit design

Cell boundary layout

Optical proximity correction and photomasks

Method of manufacturing semiconductor devices

Method of manufacturing semiconductor devices

Methods for integrated circuit design and fabrication

Conductive line routing for multi-patterning technology

Methods for integrated circuit design and fabrication

Lithographic technique for feature cut by line-end shrink

Hybrid double patterning method for semiconductor manufacture

Lithographic technique for feature cut by line-end shrink

Method of forming features with various dimensions

Method of patterning a film layer

Lithographic technique for feature cut by line-end shrink

Self aligned patterning with multiple resist layers

Optical proximity correction and photomasks

Optical proximity correction and photomasks

Method of manufacturing photo masks

Multiple patterning method for semiconductor devices

Method for checking and fixing double-patterning layout

Multiple patterning decomposition and manufacturing methods for IC

Method for making a mask with a phase bar in an integrated circuit design layout

Multiple patterning method for semiconductor devices

Methods for integrated circuit design and fabrication

Two-dimensional (2D) metal structure and method of forming the same

Method of manufacturing semiconductor devices

Two-dimensional (2D) metal structure

TAIWAN SEMICONDUCTOR MFG

Spacer etching process for integrated circuit design

Pattern modification with a preferred position function

Method of merging color sets of layout

Self-alignment for using two or more layers and methods of forming same

Conflict detection for self-aligned multiple patterning compliance

System and method for decomposition of a single photoresist mask pattern into 3 photoresist mask patterns

Method of patterning a feature of a semiconductor device

Method of decomposable checking approach for mask alignment in multiple patterning

Photo resist trimmed line end space

Self-aligned multiple patterning layout design

Conflict detection for self-aligned multiple patterning compliance

Method for checking and fixing double-patterning layout

Multi-layer metal contacts

CHEN HUANG-YU

Cell layout for multiple patterning technology

Method and apparatus for achieving multiple patterning technology compliant design layout

Layout method and system for multi-patterning integrated circuits

CHANG SHIH-MING

Semiconductor device with self-aligned interconnects and blocking portions

Semiconductor device with self-aligned interconnects

LIU RU-GUN

Method for making a mask by forming a phase bar in an integrated circuit design layout

CHEN PI-TSUNG

Decomposing integrated circuit layout

TANG YU-PO

Via-free interconnect structure with self-aligned metal line interconnections

HSIEH KEN-HSIEN

Double patterning methodology