Inventor

REDGRAVE JASON RUPERT

US68 patents

⚠️ This page may combine multiple inventors who share the name “REDGRAVE JASON RUPERT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

REDGRAVE JASON RUPERT

GOOGLE LLC

Convolutional neural network on programmable two dimensional image processor

Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register

Line buffer unit for image processor

Shift register with reduced wiring complexity

Sheet generator for image processor

Virtual linebuffers for image signal processors

Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register

Convolutional neural network on programmable two dimensional image processor

Compiler managed memory for image processor

Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register

Virtual linebuffers for image signal processors

Energy efficient processor core architecture for image processor

Compiler managed memory for image processor

Core processes for block operations on an image processor having a two-dimensional execution lane array and a two-dimensional shift register

Architecture for high performance, power efficient, programmable image processing

Macro I/O unit for image processor

Macro I/O unit for image processor

Multi-functional execution lane for image processor

Shift register with reduced wiring complexity

Convolutional neural network on programmable two dimensional image processor

Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register

Line buffer unit for image processor

Two dimensional shift array for image processor

Energy efficient processor core architecture for image processor

Sheet generator for image processor

Synchronized data chaining using on-chip cache

Synchronized data chaining using on-chip cache

Way partitioning for a system-level cache

Way partitioning for a system-level cache

Virtual linebuffers for image signal processors

Energy efficient processor core architecture for image processor

ST MICROELECTRONICS NV

Radio frequency envelope apparatus and method

Variable coder apparatus for resonant power conversion and method

Radio frequency digital-to-analog converter

Radio frequency digital-to-analog converter

Noise shaped interpolator and decimator apparatus and method

GOOGLE INC

Energy efficient processor core architecture for image processor

Two dimensional shift array for image processor

Line buffer unit for image processor

Virtual linebuffers for image signal processors

Multi-functional execution lane for image processor

IMAGINATION TECH LTD

Multistage collector for outputs in multiprocessor systems

Multistage collector for outputs in multiprocessor systems

Multistage collector for outputs in multiprocessor systems

Multistage collector for outputs in multiprocessor systems

CELESTIAL AI INC

Clock signal distribution using photonic fabric

PETERSON LUKE TILMAN

Graphics processor with non-blocking concurrent architecture

REDGRAVE JASON RUPERT

Variable-sized concurrent grouping for multiprocessing

OEZDAS CUENEYT

Systems and methods for self-intersection avoidance in ray tracing

NORSWORTHY STEVEN R

Noise shaped interpolator and decimator apparatus and method