Inventor

BAO TIEN-I

TW254 patents

⚠️ This page may combine multiple inventors who share the name “BAO TIEN-I”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BAO TIEN-I

TAIWAN SEMICONDUCTOR MFG

Spacer etching process for integrated circuit design

Method for selective growth of Cu3Ge or Cu5Si for passivation of damascene copper structures and device manufactured thereby

Method for selective growth of Cu3 Ge or Cu5 Si for passivation of damascene copper structures and device manufactured thereby

System and method for dark field inspection

Method for forming a carbon doped oxide low-k insulating layer

Method for forming damascene structure employing bi-layer carbon doped silicon nitride/carbon doped silicon oxide etch stop layer

SiOCH low k surface protection layer formation by CxHy gas plasma treatment

Methods to improve copper-fluorinated silica glass interconnects

Method for forming a hydrophilic surface on low-k dielectric insulating layers for improved adhesion

Structure and method for a low-K dielectric with pillar-type air-gaps

Lithography using high selectivity spacers for pitch reduction

Sealing pores of low-k dielectrics using CxHy

Self-aligned double spacer patterning process

Package structure and methods of forming same

Schemes for forming barrier layers for copper in interconnect structures

Scum solution for chemically amplified resist patterning in cu/low k dual damascene

Via bottom copper/barrier interface improvement to resolve via electromigration and stress migration

Semiconductor device with anchor type seal ring

Hillock inhibiting method for forming a passivated copper containing conductor layer

Low dielectric constant microelectronic conductor structure with enhanced adhesion and attenuated electrical leakage

Soft plasma oxidizing plasma method for forming carbon doped silicon containing dielectric layer with enhanced adhesive properties

Reducing CMP scratch, dishing and erosion by post CMP etch back method for low-k materials

Delamination improvement between Cu and dielectrics for damascene process

Silicon oxide dielectric material with excess silicon as diffusion barrier layer

Integration scheme for Cu/low-k interconnects

UV curing of low-k porous dielectrics

Two step post-deposition treatment of ILD layer for a lower dielectric constant and improved mechanical properties

Composite etching stop in semiconductor process integration

Microelectronic fabrication having sidewall passivated microelectronic capacitor structure fabricated therein

Solution to the problem of copper hillocks

TAIWAN SEMICONDUCTOR MFG CO LTD

Method of spacer patterning to form a target integrated circuit pattern

FinFETs and methods of forming FinFETs

Method and apparatus for forming self-aligned via with selectively deposited etching stop layer

Lithography using high selectivity spacers for pitch reduction

Interconnect structure having an etch stop layer over conductive lines

Structure and method for a low-k dielectric with pillar-type air-gaps

Interconnect structure having an etch stop layer over conductive lines

Etch damage and ESL free dual damascene metal interconnect

Method of double patterning lithography process using plurality of mandrels for integrated circuit applications

FinFETs and methods of forming FinFETs

Lithography using high selectivity spacers for pitch reduction

Semiconductor device having a porous low-k structure

Porogen bonded gap filling material in semiconductor manufacturing

Method and apparatus for forming self-aligned via with selectively deposited etching stop layer

Self-aligned double spacer patterning process

Via connection to a partially filled trench

Self-aligned interconnection structure and method

TSENG CHUN-HAO

Method of fabricating a polymer waveguide

YU CHEN-HUA

Schemes for forming barrier layers for copper in interconnect structures

SINGH SUNIL KUMAR

Etch damage and ESL free dual damascene metal interconnect