Inventor
JALAGUIER ERIC
FR17 patents
⚠️ This page may combine multiple inventors who share the name “JALAGUIER ERIC”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
COMMISSARIAT ENERGIE ATOMIQUE
11 patentsUS6974759B2Dec 13, 2005
Method for making a stacked comprising a thin film adhering to a target substrate
COMMISSARIAT ENERGIE ATOMIQUE46 citations96
US7008859B2Mar 7, 2006
Wafer and method of producing a substrate by transfer of a layer that includes foreign species
COMMISSARIAT ENERGIE ATOMIQUE33 citations91
US8679946B2Mar 25, 2014
Manufacturing process for a stacked structure comprising a thin layer bonding to a target substrate
COMMISSARIAT ENERGIE ATOMIQUE5 citations84
US7829927B2Nov 9, 2010
Polyoxometallates in memory devices
COMMISSARIAT ENERGIE ATOMIQUE13 citations83
US7031578B2Apr 18, 2006
Method and device for passive alignment of optical waveguides and optoelectronic components and optical system using said device
COMMISSARIAT ENERGIE ATOMIQUE11 citations83
US8865548B2Oct 21, 2014
Method of making a non-volatile double gate memory cell
COMMISSARIAT ENERGIE ATOMIQUE3 citations61
US7906362B2Mar 15, 2011
Assembling two substrates by molecular adhesion
COMMISSARIAT ENERGIE ATOMIQUE1 citations51
US12382845B2Aug 5, 2025
Method for manufacturing resistive memory cells
COMMISSARIAT ENERGIE ATOMIQUE0 citations47
US11711927B2Jul 25, 2023
Filamentary type non-volatile memory device
COMMISSARIAT ENERGIE ATOMIQUE0 citations44
US10002769B2Jun 19, 2018
Method for functionalizing a solid substrate, other than a substrate made of gold, via specific chemical compounds
COMMISSARIAT ENERGIE ATOMIQUE0 citations38
US10297641B2May 21, 2019
Memory device
COMMISSARIAT ENERGIE ATOMIQUE0 citations36
SOITEC SILICON ON INSULATOR
3 patentsUS7208392B1Apr 24, 2007
Creation of an electrically conducting bonding between two semi-conductor elements
SOITEC SILICON ON INSULATOR45 citations91
US7645684B2Jan 12, 2010
Wafer and method of producing a substrate by transfer of a layer that includes foreign species
SOITEC SILICON ON INSULATOR1 citations61
US7535115B2May 19, 2009
Wafer and method of producing a substrate by transfer of a layer that includes foreign species
SOITEC SILICON ON INSULATOR1 citations61