Inventor

EILERT SEAN S

US64 patents

⚠️ This page may combine multiple inventors who share the name “EILERT SEAN S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EILERT SEAN S

MICRON TECHNOLOGY INC

Signal routing between memory die and logic die

Signal routing between memory die and logic die for mode based operations

Memory device for wafer-on-wafer formed memory and logic

Mapping non-typed memory access to typed memory access

Address obfuscation for memory

Methods for performing processing-in-memory operations, and related memory devices and systems

Mapping non-typed memory access to typed memory access

Spatiotemporal fused-multiply-add, and related systems, methods and devices

Methods of performing processing-in-memory operations, and related devices and systems

Page table hooks to memory types

Memory accessing with auto-precharge

Programmable engine for data movement

Content addressable memory systems with content addressable memory buffers

Writing and querying operations in content addressable memory systems with content addressable memory buffers

Wafer-on-wafer formed memory and logic for genomic annotations

In-memory associative processing system

Data recovery system for memory devices

Programmable metadata

Input/output connections of wafer-on-wafer bonded memory and logic

Memory device with on-die cache

Testing memory of wafer-on-wafer bonded memory and logic

Signal routing between memory die and logic die for performing operations

Read replacement via data reconstruction based on access patterns

Methods for performing processing-in-memory operations, and related systems

Sequence alignment with memory arrays

Memory accessing with auto-precharge

Sequence alignment with memory arrays

Methods of performing processing-in-memory operations, and related devices and systems

Programmable engine for data movement

Adaptive parity techniques for a memory device

Memory device with on-die cache

Performing processing-in-memory operations related to spiking events, and related methods, systems and devices

Content addressable memory systems with content addressable memory buffers

Error caching techniques for improved error correction in a memory device

Error control for content-addressable memory

Methods for performing fused-multiply-add operations on serially allocated data within a processing-in-memory capable memory device, and related memory devices and systems

Memory device with multiple row buffers

Error caching techniques for improved error correction in a memory device

INTEL CORP

Method and apparatus for generating a device ID for stacked devices

High speed interface for non-volatile memory

Partitionable memory device, system, and method

Command-based control of NAND flash memory

Cluster based redundancy scheme for semiconductor memories

Method, system, and apparatus for ECC protection of small data structures

Dynamically mapping block-alterable memories

Volatile storage based power loss recovery mechanism

Flexible selection command for non-volatile memory

Logging changes to blocks in a non-volatile memory

High speed fanned out system architecture and input/output circuits for non-volatile memory

QAWAMI SHEKOUFEH

Flexible selection command for non-volatile memory