Inventor
FEGHALI WAJDI
US45 patents
⚠️ This page may combine multiple inventors who share the name “FEGHALI WAJDI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
38 patentsUS10270464B1Apr 23, 2019
Method and apparatus for high performance compression and decompression
INTEL CORP17 citations94
US8020142B2Sep 13, 2011
Hardware accelerator
INTEL CORP21 citations91
US7171604B2Jan 30, 2007
Method and apparatus for calculating cyclic redundancy check (CRC) on data using a programmable CRC engine
INTEL CORP27 citations89
US9503256B2Nov 22, 2016
SMS4 acceleration hardware
INTEL CORP11 citations84
US9047082B2Jun 2, 2015
Instruction-set architecture for programmable Cyclic Redundancy Check (CRC) computations
INTEL CORP7 citations84
US7543142B2Jun 2, 2009
Method and apparatus for performing an authentication after cipher operation in a network processor
INTEL CORP12 citations84
US7512945B2Mar 31, 2009
Method and apparatus for scheduling the processing of commands for execution by cryptographic algorithm cores in a programmable network processor
INTEL CORP14 citations84
US7607068B2Oct 20, 2009
Apparatus and method for generating a Galois-field syndrome
INTEL CORP9 citations83
US7529924B2May 5, 2009
Method and apparatus for aligning ciphered data
INTEL CORP14 citations82
US7953221B2May 31, 2011
Method for processing multiple operations
INTEL CORP15 citations81
US7872598B2Jan 18, 2011
Accelerated decompression
INTEL CORP16 citations79
US12028094B2Jul 2, 2024
Application programming interface for fine grained low latency decompression within processor core
INTEL CORP3 citations74
US11095305B1Aug 17, 2021
Method and apparatus for high performance compression and decompression
INTEL CORP2 citations73
US11681530B2Jun 20, 2023
Apparatuses, methods, and systems for hashing instructions
INTEL CORP1 citations72
US11567772B2Jan 31, 2023
Apparatuses, methods, and systems for hashing instructions
INTEL CORP1 citations72
US11494320B2Nov 8, 2022
Delayed link compression scheme
INTEL CORP2 citations72
US11188335B2Nov 30, 2021
Apparatuses, methods, and systems for hashing instructions
INTEL CORP1 citations72
US10871983B2Dec 22, 2020
Process-based multi-key total memory encryption
INTEL CORP2 citations72
US8042025B2Oct 18, 2011
Determining a message residue
INTEL CORP6 citations63
US8041945B2Oct 18, 2011
Method and apparatus for performing an authentication after cipher operation in a network processor
INTEL CORP4 citations63
US12413388B2Sep 9, 2025
Methods and apparatus to hash data
INTEL CORP0 citations62
US12182018B2Dec 31, 2024
Instruction and micro-architecture support for decompression on core
INTEL CORP0 citations62
US11455257B2Sep 27, 2022
Ultra-secure accelerators
INTEL CORP1 citations62
US7912886B2Mar 22, 2011
Configurable exponent FIFO
INTEL CORP2 citations62
US7797612B2Sep 14, 2010
Storage accelerator
INTEL CORP6 citations62
US12399718B2Aug 26, 2025
Apparatuses, methods, and systems for hashing instructions
INTEL CORP0 citations61
US7961877B2Jun 14, 2011
Factoring based modular exponentiation
INTEL CORP5 citations60
US7925011B2Apr 12, 2011
Method for simultaneous modular exponentiations
INTEL CORP5 citations60
US12537666B2Jan 27, 2026
Efficient implementation of ZUC authentication
INTEL CORP0 citations58
US10924591B2Feb 16, 2021
Low-latency link compression schemes
INTEL CORP1 citations58
US11663003B2May 30, 2023
Apparatus and method for executing Boolean functions via forming indexes to an immediate value from source register bits
INTEL CORP0 citations52
US8732548B2May 20, 2014
Instruction-set architecture for programmable cyclic redundancy check (CRC) computations
INTEL CORP0 citations52
US10824428B2Nov 3, 2020
Apparatuses, methods, and systems for hashing instructions
INTEL CORP0 citations51
US7801299B2Sep 21, 2010
Techniques for merging tables
INTEL CORP0 citations51
US12375262B2Jul 29, 2025
Fused instruction to accelerate performance of secure hash algorithm 2 (SHA-2) workloads in a graphics environment
INTEL CORP0 citations50
US11989582B2May 21, 2024
Apparatus and method for low-latency decompression acceleration via a single job descriptor
INTEL CORP0 citations50
US11955995B2Apr 9, 2024
Apparatus and method for two-stage lossless data compression, and two-stage lossless data decompression
INTEL CORP0 citations50
US8363828B2Jan 29, 2013
Diffusion and cryptographic-related operations
INTEL CORP1 citations48
SYDIR JAROSLAW J
2 patentsUS8065678B2Nov 22, 2011
Method and apparatus for scheduling the processing of commands for execution by cryptographic algorithm cores in a programmable network processor
SYDIR JAROSLAW J6 citations73
US8417943B2Apr 9, 2013
Method and apparatus for performing an authentication after cipher operation in a network processor
SYDIR JAROSLAW J2 citations58