Inventor

MASHIKO KOICHIRO

JP58 patents

⚠️ This page may combine multiple inventors who share the name “MASHIKO KOICHIRO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MASHIKO KOICHIRO

MITSUBISHI ELECTRIC CORP

Semiconductor integrated circuit having reduced current leakage and high speed

Random access memory with a plurality amplifier groups for reading and writing in normal and test modes

Gate array semiconductor device

Silicon-on-insulator circuit having series connected PMOS transistors each having connected body and gate

Semiconductor integrated circuit

Semiconductor neural network and operating method thereof

Dynamic type semiconductor memory device having an error checking and correcting circuit

Semiconductor neural network including photosensitive coupling elements

Dynamic random access memory device with staggered refresh

Random access memory device operable in a normal mode and in a test mode

Portable information equipment system

Portable information equipment system

Field programmable gate array transferring signals at high speed

Semiconductor neural network and operating method thereof

Coupling element for semiconductor neural network device

Semiconductor neural circuit device having capacitive coupling and operating method thereof

Semiconductor neural network and method of driving the same

Semiconductor memory device having error correcting circuit and method for correcting error

Semiconductor memory device

Semiconductor memory device

Latch circuit and flip-flop circuit reduced in power consumption

Gate array semiconductor integrated circuit device

Shared sense amplifier semiconductor memory

Silicon-on-insulator CMOS circuit

Semiconductor neural network and operating method thereof

Semiconductor memory device having trench and stacked polysilicon storage capacitors

CMOS row decoder circuit for use in row and column addressing

Semiconductor memory device

Semiconductor integrated circuit and consumed power reducing method

Random access memory with a plurality amplifier groups for reading and writing in normal and test modes

Coupling element for semiconductor neural network device

CMOS dynamic memory device having multiple flip-flop circuits selectively coupled to form sense amplifiers specific to neighboring data bit lines

Semiconductor memory device with word lines adjacent and non-intersecting with capacitor grooves

Dynamic random access memory having selectively activated subarrays

Semiconductor memory device having improved interconnection structure of memory cell array

Semiconductor memory

Semiconductor memory device

Dynamic random access memory

Semiconductor integrated circuit device, method for manufacturing the same, and logical circuit

SOI Semiconductor device with field shield electrode

Random access memory with plurality of amplifier groups

Random access memory with a plurality of amplifier groups

Dynamic random access memory and method for equalizing sense amplifier drive signal lines

Semiconductor memory device

Semiconductor memory device

SEMICONDUCTOR TECH ACAD RES CT

Sample hold circuit for use in time-interleaved A/D converter apparatus including paralleled low-speed pipeline A/D converters

Analog-to-digital (AD) converter and analog-to-digital conversion method

Time-to-digital converter

Band-pass Δ-Σ AD modulator for AD-converting high frequency narrow-band signal with higher precision and lower power consumption

Differential operational amplifier circuit correcting settling error for use in pipelined A/D converter