Inventor

CHUANG CHING-TE K

US20 patents

⚠️ This page may combine multiple inventors who share the name “CHUANG CHING-TE K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHUANG CHING-TE K

IBM

High-speed low-power ECL/NTL circuits with AC-coupled complementary push-pull output stage

Emitter coupled logic circuit having an active pull-down output stage

Circuits and design structures for monitoring NBTI (negative bias temperature instability) effect and/or PBTI (positive bias temperature instability) effect

Reduced integrated circuit chip leakage and method of reducing leakage

Method and system for reducing hysteresis effect in SOI CMOS circuits

High-density low-power data retention power gating with double-gate devices

Method of reducing leakage current in sub one volt SOI circuits

Method for statically timing SOI devices and circuits

Direct-coupled PNP transistor pull-up ECL circuits and direct-coupled complementary push-pull ECL circuits

Bipolar emitter-coupled logic multiplexer

Radiation hardened bipolar static RAM cell

Sense-amp based adder with source follower pass gate evaluation tree

Sense-amp based adder with source follower evaluation tree

Apparatus and method for determining the slew rate of a signal produced by an integrated circuit

Circuits and methods for characterizing device variation in electronic memory circuits

CHUANG CHING-TE K

Structure for high density stable static random access memory

High density stable static random access memory

Methods for characterizing device variation in electronic memory circuits

BANSAL ADITYA

Enhanced static random access memory stability using asymmetric access transistors and design structure for same

Enhanced static random access memory stability using asymmetric access transistors and design structure for same