Inventor

BARLOW GEORGE J

US46 patents

⚠️ This page may combine multiple inventors who share the name “BARLOW GEORGE J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BARLOW GEORGE J

BULL HN INFORMATION SYST

Recovery method and apparatus for a pipelined processing unit of a multiprocessor system

Cache resiliency in processing a variety of address faults

Method and apparatus for limiting the utilization of an asynchronous bus with distributed controlled access

Multiprocessor system with centralized initialization, testing and monitoring of the system and providing centralized timing

Apparatus and method for providing more effective reiterations of interrupt requests in a multiprocessor system

Means for providing a graceful power shut-down capability in a multiprocessor system having certain processors not inherently having a power shut-down capability

Data processing system with a fast interrupt

Apparatus for loading and verifying a control store memory of a central subsystem

Apparatus and method for interprocessor communication

Method and apparatus for memory retry

Synchronous cache memory system incorporating tie-breaker apparatus for maintaining cache coherency using a duplicate directory

Programmable system bus priority network

Apparatus and method for providing more effective reiterations of processing task requests in a multiprocessor system

Method and apparatus for a high performance round robin distributed bus priority network

Cancel mechanism for resilient resource management and control

Flexible distributed bus priority network

Bidirectional control signalling bus interface apparatus for transmitting signals between two bus systems

Inter and intra priority resolution network for an asynchronous bus system

Data processing system having a bus command generated by one subsystem on behalf of another subsystem

Method and apparatus for performing health tests of units of a data processing system

Method and apparatus for resetting a memory upon power recovery

Minimum contention processor and system bus system

HONEYWELL INF SYSTEMS

Interface for controlling information transfers between main data processing systems units and a central subsystem

Data processing system having distributed priority network

Data processing system providing locked operation of shared resources

Diagnostic testing apparatus and method

Apparatus for processing data transfer requests in a data processing system

Pause apparatus for a memory controller with interleaved queuing apparatus

Data processing system having distributed priority network with logic for deactivating information transfer requests

Apparatus and method for storing parity encoded data from a plurality of input/output sources

Modularly addressable units coupled in a data processing system over a common bus

Data processing system having a data integrity technique

Intersystem transaction identification logic

Retry method and apparatus for use in a magnetic recording and reproducing system

Diagnostic subsystem for a cache memory

Error detection and correction locator circuits

Intersystem communication link

Channel number priority assignment apparatus

Logic board interlock indication apparatus

Memory delay start apparatus for a queued memory controller

Error detection apparatus for verifying binary coded constants

HONEYWELL BULL

Resilient bus system

Resilient bus system

Read in process memory apparatus

Address transform method and apparatus for transferring addresses

Multiprocessor level change synchronization apparatus