Inventor

AGRAWAL OM P

US127 patents

⚠️ This page may combine multiple inventors who share the name “AGRAWAL OM P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AGRAWAL OM P

ADVANCED MICRO DEVICES INC

Flexible synchronous/asynchronous cell structure for a high density programmable logic device

Logic allocator for a programmable logic device

Programmable gate array device having cascaded means for function definition

Programmable gate array with improved interconnect structure, input/output structure and configurable logic block

Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices

Programmable gate array with logic cells having symmetrical input/output structures

An I/O macrocell for a programmable logic device

Array of configurable logic blocks each including a look up table having inputs coupled to a first multiplexer and having outputs coupled to a second multiplexer

Array of configurable logic blocks including cascadable lookup tables

Programmable gate array with improved interconnect structure, input/output structure and configurable logic block

Programmable gate array with improved interconnect structure

Multiple array high performance programmable logic device family

Programmable uniform symmetrical distribution logic allocator for a high-density complex PLD

Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses

Array of configurable logic blocks including network means for broadcasting clock signals to different pluralities of logic blocks

Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexible logic allocation

Constant delay interconnect for coupling configurable logic blocks

Programmable gate array with improved interconnect structure, input/output structure and configurable logic block

Programmable system synchronizer

Programmable gate array with improved configurable logic block

Interconnect structure for programmable logic device

Programmable gate array with logic cells having configurable output enable

Flexible, programmable cell array interconnected by a programmable switch matrix

High density programmable logic device

Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix

Programmable logic array using internally generated dynamic logic signals as selection signals for controlling its functions

LATTICE SEMICONDUCTOR CORP

FPGA with register-intensive architecture

Variable grain architecture for FPGA integrated circuits

Non-volatile and reconfigurable programmable logic devices

Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation and methods of use

Scalable architecture for high density CPLD&#39;s having two-level hierarchy of routing resources

Scalable architecture for high density CPLDS having two-level hierarchy of routing resources

Methods for configuring FPGA&#39;s having variable grain components for providing time-shared access to interconnect resources

Scalable serializer-deserializer architecture and programmable interface

High speed interface for a programmable interconnect circuit

Clock generator

I/O block for a programmable interconnect circuit

FPGA integrated circuit having embedded sram memory blocks each with statically and dynamically controllable read mode

Programmable input/output block (IOB) in FPGA integrated circuits

VANTIS CORP

Symmetrical, extended and fast direct connections between variable grain blocks in FPGA integrated circuits

Efficient interconnect network for use in FPGA device having variable grain architecture

Synthesis-friendly FPGA architecture with variable length and variable timing interconnect

Electrically erasable and reprogrammable, nonvolatile integrated storage device with in-system programming and verification (ISPAV) capabilities for supporting in-system reconfiguring of PLD&#39;s

FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals

Variable grain architecture for FPGA integrated circuits

Methods for configuring FPGA&#39;s having variable grain components for providing time-shared access to interconnect resources

FPGA device and method that includes a variable grain function architecture for implementing configuration logic blocks and a complimentary variable length interconnect architecture for providing configurable routing between configuration logic blocks

Tileable and compact layout for super variable grain blocks within FPGA device

Dual port SRAM memory for run time use in FPGA integrated circuits

FPGA integrated circuit having embedded SRAM memory blocks with registered address and data input sections

Scalable architecture for high density CPLD's having two-level hierarchy of routing resources

Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources

Electrically erasable and reprogrammable, nonvolatile integrated storage device with in-system programming and verification (ISPAV) capabilities for supporting in-system reconfiguring of PLD's

Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources