P

Inventor

ECKERT MARTIN

DE57 patents
⚠️ This page may combine multiple inventors who share the name “ECKERT MARTIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

32 patents
US10345136B2Jul 9, 2019

Adjustable load transmitter

IBM4 citations83
US10146144B1Dec 4, 2018

Adjustable load transmitter

IBM5 citations83
US10082526B1Sep 25, 2018

Probe card alignment

IBM8 citations83
US10082419B1Sep 25, 2018

Adjustable load transmitter

IBM8 citations83
US9401222B1Jul 26, 2016

Determining categories for memory fail conditions

IBM9 citations80
US6341093B1Jan 22, 2002

SOI array sense and write margin qualification

IBM11 citations74
US9892789B1Feb 13, 2018

Content addressable memory with match hit quality indication

IBM3 citations73
US10605649B2Mar 31, 2020

Adjustable load transmitter

IBM1 citations72
US10527649B2Jan 7, 2020

Probe card alignment

IBM1 citations72
US10422817B2Sep 24, 2019

Probe card alignment

IBM1 citations72
US9740813B1Aug 22, 2017

Layout effect characterization for integrated circuits

IBM4 citations72
US9885748B2Feb 6, 2018

Module testing utilizing wafer probe test equipment

IBM2 citations71
US9496188B2Nov 15, 2016

Soldering three dimensional integrated circuits

IBM3 citations71
US9977053B2May 22, 2018

Wafer probe alignment

IBM4 citations69
US9927463B2Mar 27, 2018

Wafer probe alignment

IBM2 citations69
US11262381B2Mar 1, 2022

Device for positioning a semiconductor die in a wafer prober

IBM2 citations66
US10955440B2Mar 23, 2021

Probe card alignment

IBM0 citations62
US11209479B2Dec 28, 2021

Stressing integrated circuits using a radiation source

IBM0 citations61
US7466716B2Dec 16, 2008

Reducing latency in a channel adapter by accelerated I/O control block processing

IBM4 citations59
US10614884B2Apr 7, 2020

Content addressable memory with match hit quality indication

IBM0 citations52
US10347337B2Jul 9, 2019

Content addressable memory with match hit quality indication

IBM0 citations52
US7092310B2Aug 15, 2006

Memory array with multiple read ports

IBM0 citations52
US10114914B2Oct 30, 2018

Layout effect characterization for integrated circuits

IBM0 citations51
US9904748B1Feb 27, 2018

Layout effect characterization for integrated circuits

IBM0 citations51
US9627090B1Apr 18, 2017

RAM at speed flexible timing and setup control

IBM0 citations51
US9627017B1Apr 18, 2017

RAM at speed flexible timing and setup control

IBM0 citations51
US11239152B2Feb 1, 2022

Integrated circuit with optical tunnel

IBM0 citations50
US10114069B2Oct 30, 2018

Method for electrical testing of a 3-D chip stack

IBM0 citations50
US10056346B2Aug 21, 2018

Chip attach frame

IBM0 citations50
US9891272B2Feb 13, 2018

Module testing utilizing wafer probe test equipment

IBM0 citations50
US9686895B2Jun 20, 2017

Chip attach frame

IBM0 citations50
US9250289B2Feb 2, 2016

System for electrical testing and manufacturing of a 3-D chip stack and method

IBM0 citations50

LUK LAMELLEN & KUPPLUNGSBAU

5 patents

ECKERT MARTIN

4 patents

SIRONA DENTAL SYSTEMS GMBH

2 patents

RUNGE FRED

2 patents

DEUTSCHE TELEKOM AG

1 patent

GLOBALFOUNDRIES INC

1 patent

YAHOO INC

1 patent

BUECHNER THOMAS

1 patent

AXNIX CHRISTINE

1 patent

Showing the top 50 of 57 patents by PatentIndex Score.