Inventor

PILLE JUERGEN

DE64 patents

⚠️ This page may combine multiple inventors who share the name “PILLE JUERGEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PILLE JUERGEN

IBM

SOI transistor with body contact and method of forming same

Single-ended read and differential write scheme

Read/write alignment scheme for port reduction of multi-port SRAM cells

Storage cell with integrated soft error detection and correction

Level shifter for boosting wordline voltage and memory cell performance

Method and system for pipeline reduction

Method to reduce leakage of a SRAM-array

Hierarchical priority filter with integrated serialization for determining the entry with the highest priority in a buffer memory

Current-mode sense amplifier

Single ended bitline current sense amplifier for SRAM applications

SOI array sense and write margin qualification

Wordline booster circuit and method of operating a wordline booster circuit

Receiving latch with hysteresis

Static wordline redundancy memory device

Microelectronic device with a memory element utilizing stacked vertical devices

Buried conductive layer supplying digital circuits

Current-mode sense amplifier

Memory block erasure

Memory block erasure

Power saving by disabling cyclic bitline precharge

Build synthesized soft arrays

Activation of memory core circuits in an integrated circuit

Activation of memory core circuits in an integrated circuit

Fast single ended sensing with configurable half-latch

Progamable control clock circuit for arrays

Functional float mode screen to test for leakage defects on SRAM bitlines

Redundancy in signal distribution trees

Redundancy in signal distribution trees

Dynamic adjustment of signal delay with memory array voltage

Wordline booster design structure and method of operating a wordine booster circuit

Automatic method for routing and designing an LSI

Methods and apparatus for accessing memory

Static logic compatible multiport latch

Restore function for memory cells using negative bitline-selection

Integrated circuit including logic circuitry

Stressing integrated circuits using a radiation source

Test interface for memory elements

Design structure for improving performance of SRAM cells, SRAM cell, SRAM array, and write circuit

Method to improve performance of SRAM cells, SRAM cell, SRAM array, and write circuit

Device and method for decoding an address word into word-line signals

Advanced array local clock buffer base block circuit

Transforming a phase-locked-loop generated chip clock signal to a local clock signal

Transforming a phase-locked-loop generated chip clock signal to a local clock signal

Memory array with multiple read ports

Multiple port memory apparatus

Erasing a partition of an SRAM array with hardware support

Semiconductor circuit including an initialization circuit for initializing memory cells and clearing of relatively large blocks of memory

Integrated circuit with vertical structures on nodes of a grid

DENGLER OSAMA

Boost circuit for generating an adjustable boost voltage

CHAN YUEN H

Low power programmable clock delay generator with integrated decode function