Inventor
YANES ADALBERTO G
US25 patents
⚠️ This page may combine multiple inventors who share the name “YANES ADALBERTO G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
21 patentsUS5577236ANov 19, 1996
Memory controller for reading data from synchronous RAM
IBM225 citations96
US9483350B1Nov 1, 2016
Flash memory codeword architectures
IBM25 citations94
US5463752AOct 31, 1995
Method and system for enhancing the efficiency of communication between multiple direct access storage devices and a storage system controller
IBM31 citations92
US5202998AApr 13, 1993
Fast, simultaneous multi-processor system status communication interface
IBM37 citations92
US6038676AMar 14, 2000
Method and circuit for data integrity verification during DASD data transfer
IBM32 citations89
US5452421ASep 19, 1995
System for using register sets and state machines sets to communicate between storage controller and devices by using failure condition activity defined in a request
IBM28 citations88
US5533194AJul 2, 1996
Hardware-assisted high speed memory test apparatus and method
IBM42 citations87
US9652157B2May 16, 2017
Accelerated non-volatile memory recirculation processing
IBM6 citations84
US10489086B1Nov 26, 2019
Reducing read errors by performing mitigation reads to blocks of non-volatile memory
IBM7 citations82
US5461720AOct 24, 1995
System for increasing the efficiency of communications between controller and plurality of host computers by prohibiting retransmission of the same message for predetermined period of time
IBM7 citations74
US10229076B2Mar 12, 2019
Peripheral component interconnect express (PCIE) pseudo-virtual channels using vendor defined messages
IBM2 citations73
US9811419B2Nov 7, 2017
Validation bits and offsets to represent logical pages split between data containers
IBM2 citations73
US6931473B2Aug 16, 2005
Data transfer via Host/PCI-X bridges
IBM9 citations71
US10770155B2Sep 8, 2020
Determining a read apparent voltage infector page and infected page
IBM2 citations70
US11086565B2Aug 10, 2021
Reducing effects of read array operations of read apparent voltage
IBM0 citations60
US6038620AMar 14, 2000
Method and system for optimal high speed match in a high performance controller which ensures an input/output interface stays ahead of a host interface
IBM5 citations58
US10133694B2Nov 20, 2018
Peripheral component interconnect express (PCIE) pseudo-virtual channels using vendor defined messages
IBM0 citations52
US9971517B2May 15, 2018
Accelerated non-volatile memory recirculation processing
IBM0 citations52
US9946594B2Apr 17, 2018
Validation bits and offsets to represent logical pages split between data containers
IBM0 citations52
US9875153B2Jan 23, 2018
Validation bits and offsets to represent logical pages split between data containers
IBM0 citations52
US8364879B2Jan 29, 2013
Hierarchical to physical memory mapped input/output translation
IBM1 citations52