Inventor

INGALLS CHARLES L

US113 patents

⚠️ This page may combine multiple inventors who share the name “INGALLS CHARLES L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INGALLS CHARLES L

MICRON TECHNOLOGY INC

Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell

Three-dimensional container diode for use with multi-state material in a non-volatile memory cell

Reprogrammable non-volatile ferroelectric latch for use with a memory controller

Array data bit inversion

Open digit line array architecture for a memory array

Word line driver for negative voltage

Three-dimensional container diode for use with multi-state material in a non-volatile memory cell

On-chip circuit and method for testing memory devices

Three-dimensional container diode for use with multi-state material in a non-volatile memory cell

Method and apparatus for strobing antifuse circuits in a memory device

Programmable bandwidth I/O port and a communication interface using the same port having a plurality of serial access memories capable of being configured for a variety of protocols

Controlling synchronous serial access to a multiport memory

Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell

Memory circuit with local isolation and pre-charge circuits

Method and apparatus for strobing antifuse circuits in a memory device

Method and apparatus for initializing a memory device

Method and apparatus for strobing antifuse circuits in a memory device

Shared data lines for memory write and memory test operations

Open digit line array architecture for a memory array

On-chip circuit and method for testing memory devices

Method and apparatus for a high speed cyclical redundancy check system

Controlling synchronous serial access to a multiport memory

Apparatuses and methods for reducing row address to column address delay

Array data bit inversion

Array data bit inversion

Integrated assemblies having sense-amplifier-circuitry distributed amongst two or more locations, and having circuitry configured to isolate local column-select-structures from a global structure

Integrated components which have both horizontally-oriented transistors and vertically-oriented transistors

Array data bit inversion

Integrated memory assemblies comprising multiple memory array decks

Half density ferroelectric memory and operation

Sense amplifier constructions

Array data bit inversion

Plate defect mitigation techniques

Low voltage sense amplifier and sensing method

Word line driver for negative voltage

Single ended data bus equilibration scheme

Equilibration/pre-charge circuit for a memory device

Three dimensional memory devices

System having multiple subsystems and test signal source resident upon common substrate

Open digit line array architecture for a memory array

Open digit line array architecture for a memory array

System and method to counteract voltage disturbances in open digitline array dynamic random access memory systems

Latched row or column select enable driver

Latched row or column select enable driver

Voltage-dependent delay

Method and apparatus for global testing the impedance of a programmable element

Integrated memory comprising secondary access devices between digit lines and primary access devices

MICRON SEMICONDUCTOR INC

Test signal generator on substrate to test

KIM TAE

Memory device word line drivers and methods

THOMPSON J WAYNE

Transistor voltage threshold mismatch compensated sense amplifiers and methods for precharging sense amplifiers