Inventor
GARDNER MARK
US17 patents
⚠️ This page may combine multiple inventors who share the name “GARDNER MARK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TOKYO ELECTRON LTD
6 patentsUS11557655B2Jan 17, 2023
Device and method of forming with three-dimensional memory and three-dimensional logic
TOKYO ELECTRON LTD2 citations73
US11264289B2Mar 1, 2022
Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacks
TOKYO ELECTRON LTD2 citations73
US12218011B2Feb 4, 2025
Method of making 3D segmented devices for enhanced 3D circuit density
TOKYO ELECTRON LTD0 citations62
US12020990B2Jun 25, 2024
Method for threshold voltage tuning through selective deposition of high-k metal gate (HKMG) film stacks
TOKYO ELECTRON LTD0 citations62
US11764200B2Sep 19, 2023
High density architecture design for 3D logic and 3D memory circuits
TOKYO ELECTRON LTD0 citations62
US11264285B2Mar 1, 2022
Method for forming film stacks with multiple planes of transistors having different transistor architectures
TOKYO ELECTRON LTD1 citations59
ADVANCED MICRO DEVICES INC
3 patentsUS6150695ANov 21, 2000
Multilevel transistor formation employing a local substrate formed within a shallow trench
ADVANCED MICRO DEVICES INC10 citations74
US6159814ADec 12, 2000
Spacer formation by poly stack dopant profile design
ADVANCED MICRO DEVICES INC9 citations72
US6096615AAug 1, 2000
Method of forming a semiconductor device having narrow gate electrode
ADVANCED MICRO DEVICES INC6 citations62