Inventor
KUTTANNA BELLIAPPA MANAVATTIRA
US8 patents
Patents
8 patentsUS6269427B1Jul 31, 2001
Multiple load miss handling in a cache memory system
IBM77 citations95
US5737751AApr 7, 1998
Cache memory management system having reduced reloads to a second level cache for enhanced memory performance in a data processing system
IBM29 citations92
US6321303B1Nov 20, 2001
Dynamically modifying queued transactions in a cache memory system
IBM22 citations91
US5873123AFeb 16, 1999
Processor and method for translating a nonphysical address into a physical address utilizing a selectively nonsequential search of page table entries
IBM39 citations89
US5787479AJul 28, 1998
Method and system for preventing information corruption in a cache memory caused by an occurrence of a bus error during a linefill operation
IBM17 citations83
US5974505AOct 26, 1999
Method and system for reducing power consumption of a non-blocking cache within a data processing system
IBM15 citations73
US5721867AFeb 24, 1998
Method and apparatus for executing single beat write store instructions during a cache store linefill operation
IBM7 citations73
US6311254B1Oct 30, 2001
Multiple store miss handling in a cache memory memory system
IBM4 citations62