Inventor
SOININEN PEKKA JUHA
FI18 patents
⚠️ This page may combine multiple inventors who share the name “SOININEN PEKKA JUHA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ASM INT
10 patentsUS7601223B2Oct 13, 2009
Showerhead assembly and ALD methods
ASM INT607 citations99
US7241677B2Jul 10, 2007
Process for producing integrated circuits including reduction using gaseous organic compounds
ASM INT119 citations99
US7144809B2Dec 5, 2006
Production of elemental films using a boron-containing reducing agent
ASM INT450 citations99
US6902763B1Jun 7, 2005
Method for depositing nanolaminate thin films on sensitive surfaces
ASM INT191 citations99
US6821889B2Nov 23, 2004
Production of elemental thin films using a boron-containing reducing agent
ASM INT349 citations99
US6800552B2Oct 5, 2004
Deposition of transition metal carbides
ASM INT91 citations99
US6863727B1Mar 8, 2005
Method of depositing transition metal nitride thin films
ASM INT87 citations95
US7749871B2Jul 6, 2010
Method for depositing nanolaminate thin films on sensitive surfaces
ASM INT34 citations92
US7485340B2Feb 3, 2009
Production of elemental films using a boron-containing reducing agent
ASM INT26 citations92
US7329590B2Feb 12, 2008
Method for depositing nanolaminate thin films on sensitive surfaces
ASM INT35 citations92
ASM MICROCHEMISTRY OY
3 patentsUS6599572B2Jul 29, 2003
Process for growing metalloid thin films utilizing boron-containing reducing agents
ASM MICROCHEMISTRY OY233 citations99
US6482262B1Nov 19, 2002
Deposition of transition metal carbides
ASM MICROCHEMISTRY OY328 citations99
US6475276B1Nov 5, 2002
Production of elemental thin films using a boron-containing reducing agent
ASM MICROCHEMISTRY OY864 citations99
ASM INTERNAT NV
2 patentsIMEC INTER UNI MICRO ELECTR
2 patentsUS6391785B1May 21, 2002
Method for bottomless deposition of barrier layers in integrated circuit metallization schemes
IMEC INTER UNI MICRO ELECTR584 citations98
US6664192B2Dec 16, 2003
Method for bottomless deposition of barrier layers in integrated circuit metallization schemes
IMEC INTER UNI MICRO ELECTR77 citations97