Inventor
LEE BRIAN S
TW23 patents
⚠️ This page may combine multiple inventors who share the name “LEE BRIAN S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
PROMOS TECHNOLOGIES INC
10 patentsUS6770954B2Aug 3, 2004
Semiconductor device with SI-GE layer-containing low resistance, tunable contact
PROMOS TECHNOLOGIES INC26 citations92
US6703279B2Mar 9, 2004
Semiconductor device having contact of Si-Ge combined with cobalt silicide
PROMOS TECHNOLOGIES INC31 citations92
US6521956B1Feb 18, 2003
Semiconductor device having contact of Si-Ge combined with cobalt silicide
PROMOS TECHNOLOGIES INC29 citations92
US6511905B1Jan 28, 2003
Semiconductor device with Si-Ge layer-containing low resistance, tunable contact
PROMOS TECHNOLOGIES INC36 citations92
US6818515B1Nov 16, 2004
Method for fabricating semiconductor device with loop line pattern structure
PROMOS TECHNOLOGIES INC31 citations91
US6566190B2May 20, 2003
Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory devices
PROMOS TECHNOLOGIES INC20 citations84
US6544888B2Apr 8, 2003
Advanced contact integration scheme for deep-sub-150 nm devices
PROMOS TECHNOLOGIES INC17 citations84
US6828615B2Dec 7, 2004
Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory devices
PROMOS TECHNOLOGIES INC10 citations74
US7087947B2Aug 8, 2006
Semiconductor device with loop line pattern structure, method and alternating phase shift mask for fabricating the same
PROMOS TECHNOLOGIES INC4 citations61
US7402364B2Jul 22, 2008
Semiconductor device with loop line pattern structure, method and alternating phase shift mask for fabricating the same
PROMOS TECHNOLOGIES INC0 citations51
INFINEON TECHNOLOGIES AG
7 patentsUS6939763B2Sep 6, 2005
DRAM cell arrangement with vertical MOS transistors, and method for its fabrication
INFINEON TECHNOLOGIES AG43 citations92
US6426253B1Jul 30, 2002
Method of forming a vertically oriented device in an integrated circuit
INFINEON TECHNOLOGIES AG49 citations92
US6335247B1Jan 1, 2002
Integrated circuit vertical trench device and method of forming thereof
INFINEON TECHNOLOGIES AG25 citations92
US6362040B1Mar 26, 2002
Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates
INFINEON TECHNOLOGIES AG41 citations90
US6475859B1Nov 5, 2002
Plasma doping for DRAM with deep trenches and hemispherical grains
INFINEON TECHNOLOGIES AG10 citations74
US6372567B1Apr 16, 2002
Control of oxide thickness in vertical transistor structures
INFINEON TECHNOLOGIES AG10 citations74
US7329916B2Feb 12, 2008
DRAM cell arrangement with vertical MOS transistors
INFINEON TECHNOLOGIES AG3 citations63
IBM
3 patentsUS6284666B1Sep 4, 2001
Method of reducing RIE lag for deep trench silicon etching
IBM87 citations95
US6150670ANov 21, 2000
Process for fabricating a uniform gate oxide of a vertical transistor
IBM22 citations92
US6348388B1Feb 19, 2002
Process for fabricating a uniform gate oxide of a vertical transistor
IBM12 citations73