Inventor

MEYER DERRICK R

US45 patents

⚠️ This page may combine multiple inventors who share the name “MEYER DERRICK R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MEYER DERRICK R

ADVANCED MICRO DEVICES INC

Maintaining cache coherency during a memory read operation in a multiprocessing computer system

Message based power management in a multi-processor system

Message based power management

Messaging scheme to maintain cache coherency and conserve system memory bandwidth during a memory read operation in a multiprocessing computer system

Store to load forwarding using a dependency link file

Use of a signal line to adjust width and/or frequency of a communication link during system operation

System and method of increasing bandwidth for issuing ordered transactions into a distributed communication system

System for reconfiguring a first device and/or a second device to use a maximum compatible communication parameters based on transmitting a communication to the first and second devices of a point-to-point link

System and method for initiating a serial data transfer between two clock domains

Snoop resynchronization mechanism to preserve read ordering

System and method for initiating a serial data transfer between two clock domains

Virtual channels and corresponding buffer allocations for deadlock-free computer system operation

Computer system implementing a system and method for ordering input/output (IO) memory operations within a coherent portion thereof

Computer system implementing system and method for ordering write operations and maintaining memory coherency

Floating point stack manipulation using a register map and speculative top of stack values

Floating point unit using a central window for storing instructions capable of executing multiple instructions in a single clock cycle

Implementing locks in a distributed processing system

System and method of initializing and determining a bootstrap processor [BSP] in a fabric of a distributed multiprocessor computing system

Store to load forwarding using a dependency link file

Method and apparatus for controlling power management state transitions between devices connected via a clock forwarded interface

Apparatus and method for superforwarding load operands in a microprocessor

Method to transfer data in a system with multiple clock domains using clock skipping techniques

Rapid execution of floating point load control word instructions

Collation of interrupt control devices

Method and mechanism for generating a clock signal with a relatively linear increase or decrease in clock frequency

Response virtual channel for handling all responses

Host bridge translating non-coherent packets from non-coherent link to coherent packets on conherent link and vice versa

Deadlock avoidance using exponential backoff

System and method for initializing source-synchronous data transfers using ratio bits

Minimizing use of bus command code points to request the start and end of a lock

System and method using selection logic units to define stack orders

Apparatus for exchanging two stack registers

System and method for initiating an operating frequency using dual-use signal lines

COMPAQ INFORMATION TECHNOLOGIE

Implementation of a conditional move instruction in an out-of-order processor

Data cache having store queue bypass for out-of-order instruction execution and method for same

Methods and apparatus for processing load instructions in the presence of RAM array and data bus conflicts

Method for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list

HEWLETT PACKARD DEVELOPMENT CO

Method and apparatus for determining availability of a queue to which a program step is issued out of program order

Method and apparatus for determining availability of a queue which allows random insertion

Apparatus for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list

DIGITAL EQUIPMENT CORP

Error transition mode for multi-processor system

Method and apparatus for maximizing utilization of an internal processor bus in the context of external transactions running at speeds fractionally greater than internal transaction times

COMPAQ COMPUTER CORP

Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol

Method and apparatus for a dedicated physically indexed copy of the data cache tag arrays

API NETWORKS INC

System and method of maintaining coherency in a distributed communication system