Inventor
SANDON PETER A
US38 patents
⚠️ This page may combine multiple inventors who share the name “SANDON PETER A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
26 patentsUS7127560B2Oct 24, 2006
Method of dynamically controlling cache size
IBM81 citations96
US7426674B2Sep 16, 2008
Method of computing partial CRCs
IBM20 citations92
US7185215B2Feb 27, 2007
Machine code builder derived power consumption reduction
IBM32 citations92
US7010469B2Mar 7, 2006
Method of computing partial CRCs
IBM18 citations92
US6794901B2Sep 21, 2004
Apparatus for reducing soft errors in dynamic circuits
IBM33 citations92
US6591361B1Jul 8, 2003
Method and apparatus for converting data into different ordinal types
IBM21 citations92
US7386703B2Jun 10, 2008
Two dimensional addressing of a matrix-vector register array
IBM14 citations91
US7941772B2May 10, 2011
Dynamic critical path detector for digital logic circuit paths
IBM10 citations84
US7962695B2Jun 14, 2011
Method and system for integrating SRAM and DRAM architecture in set associative cache
IBM14 citations83
US7249358B2Jul 24, 2007
Method and apparatus for dynamically allocating processors
IBM12 citations83
US8988139B2Mar 24, 2015
Self-selected variable power integrated circuit
IBM11 citations82
US7949853B2May 24, 2011
Two dimensional addressing of a matrix-vector register array
IBM12 citations82
US11165766B2Nov 2, 2021
Implementing authentication protocol for merging multiple server nodes with trusted platform modules utilizing provisioned node certificates to support concurrent node add and remove
IBM2 citations72
US7865749B2Jan 4, 2011
Method and apparatus for dynamic system-level frequency scaling
IBM5 citations63
US8024513B2Sep 20, 2011
Method and system for implementing dynamic refresh protocols for DRAM based cache
IBM5 citations62
US7882302B2Feb 1, 2011
Method and system for implementing prioritized refresh of DRAM based cache
IBM5 citations62
US6112300AAug 29, 2000
Method and apparatus for performing multi-way branching using a hardware relational table
IBM6 citations62
US7496731B2Feb 24, 2009
Two dimensional addressing of a matrix-vector register array
IBM2 citations61
US6989696B2Jan 24, 2006
System and method for synchronizing divide-by counters
IBM3 citations61
US10824953B2Nov 3, 2020
Reconfigurable array processor for pattern matching
IBM0 citations52
US10824952B2Nov 3, 2020
Reconfigurable array processor for pattern matching
IBM0 citations52
US9189380B2Nov 17, 2015
Systems and methods to save and restore a write gather pipe
IBM0 citations52
US8019970B2Sep 13, 2011
Three-dimensional networking design structure
IBM0 citations52
US7971122B2Jun 28, 2011
Method of computing partial CRCS
IBM0 citations52
US7865694B2Jan 4, 2011
Three-dimensional networking structure
IBM0 citations52
US9779258B2Oct 3, 2017
Confidential extraction of system internal data
IBM0 citations42
NINTENDO CO LTD
8 patentsUS6571328B2May 27, 2003
Method and apparatus for obtaining a scalar value directly from a vector register
NINTENDO CO LTD139 citations99
US7908460B2Mar 15, 2011
Method and apparatus for obtaining a scalar value directly from a vector register
NINTENDO CO LTD34 citations96
US6701424B1Mar 2, 2004
Method and apparatus for efficient loading and storing of vectors
NINTENDO CO LTD44 citations96
US6859862B1Feb 22, 2005
Method and apparatus for software management of on-chip cache
NINTENDO CO LTD37 citations92
US6857061B1Feb 15, 2005
Method and apparatus for obtaining a scalar value directly from a vector register
NINTENDO CO LTD22 citations92
US6681296B2Jan 20, 2004
Method and apparatus for software management of on-chip cache
NINTENDO CO LTD39 citations92
US7739480B2Jun 15, 2010
Method and apparatus for obtaining a scalar value directly from a vector register
NINTENDO CO LTD6 citations74
US7581084B2Aug 25, 2009
Method and apparatus for efficient loading and storing of vectors
NINTENDO CO LTD5 citations73
BUETI SERAFINO
2 patentsUS8132136B2Mar 6, 2012
Dynamic critical path detector for digital logic circuit paths
BUETI SERAFINO7 citations82
US8291357B2Oct 16, 2012
On-chip identification circuit incorporating pairs of conductors, each having an essentially random chance of being shorted together as a result of process variations
BUETI SERAFINO5 citations60