Inventor

ANDIDEH EBRAHIM

US70 patents

⚠️ This page may combine multiple inventors who share the name “ANDIDEH EBRAHIM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ANDIDEH EBRAHIM

INTEL CORP

Interlayer dielectric with a composite dielectric stack

Interlayer dielectric with a composite dielectric stack

Device structure and method for reducing silicide encroachment

Structure and process flow for fabrication of dual gate floating body integrated MOS transistors

Method of making a semiconductor device using a silicon carbide hard mask

Process for filling submicron spaces with dielectric

Semiconductor device having deposited silicon regions and a method of fabrication

Structure and process flow for fabrication of dual gate floating body integrated MOS transistors

Shielded channel transistor structure with embedded source/drain junctions

Method of fabricating a MOS transistor with a raised source/drain extension

Device structure and method for reducing silicide encroachment

Device structure and method for reducing silicide encroachment

Method for making a semiconductor device having a low-k dielectric layer

Method for preparing carbon doped oxide insulating layers

Low-dielectric constant structure with a multilayer stack of thin films with pores

Method for making a semiconductor device that has a dual damascene interconnect

Interlayer dielectric with a composite dielectric stack

Process for forming doped regions from solid phase diffusion source

Laminating magnetic materials in a semiconductor device

Polish pad with non-uniform groove depth to improve wafer polish rate uniformity

Semiconductor device having a low-K dielectric layer

Plasma induced depletion of fluorine from surfaces of fluorinated low-k dielectric materials

Shielded channel transistor structure with embedded source/drain junctions

Method for making a semiconductor device having a carbon doped oxide insulating layer

Polish pad with non-uniform groove depth to improve wafer polish rate uniformity

Elimination of pad conditioning in a chemical mechanical polishing process

Carbon doped oxide deposition

Method of forming a carbon doped oxide layer on a substrate

Method of forming a semiconductor device using a carbon doped oxide layer to control the chemical mechanical polishing of a dielectric layer

Enhanced surface modification of low K carbon-doped oxide

PECVD air gap integration

Method for increasing ferroelectric characteristics of polymer memory cells

Method of making a semiconductor device by converting a hydrophobic surface of a dielectric layer to a hydrophilic surface

Method and apparatus for filling interlayer vias on ferroelectric polymer substrates

Ferroelectric memory device with a conductive polymer layer and a method of formation

Concentration graded carbon doped oxide

Method to avoid via poisoning in dual damascene process

Method of making an on-die decoupling capacitor for a semiconductor device

Method for making a sub 100 nanometer semiconductor device using conventional lithography steps

Plasma induced depletion of fluorine from surfaces of fluorinated low-k dielectric materials

Method of reducing the surface roughness of spin coated polymer films

Methods of providing dielectric to conductor adhesion in package structures

Method of forming a semiconductor device using a carbon doped oxide layer to control the chemical mechanical polishing of a dielectric layer

Ferroelectric memory device with a conductive polymer layer and a method of formation

Parallel electrode memory

Ferroelectric memory device with a conductive polymer layer and a method of formation

Method of making a semiconductor device that includes a dual damascene interconnect

Plasma ashing process for removing photoresist and residues during ferroelectric device fabrication

TEH WENG HONG

Bumpless build-up layer (BBUL) semiconductor package with ultra-thin dielectric layer

QORVO US INC

Wafer-level-packaged BAW devices with surface mount connection structures