Inventor

ALFIERI ROBERT A

US42 patents

⚠️ This page may combine multiple inventors who share the name “ALFIERI ROBERT A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ALFIERI ROBERT A

NVIDIA CORP

Method and apparatus for performing network processing functions

Internet protocol (IP) router residing in a processor chipset

Method and apparatus for providing an integrated file system

Network level protocol negotiation and operation

Network processing pipeline chipset for routing and host packet processing

Building integrated circuits using a common database

Method and apparatus for performing network processing functions

Watchdog monitoring for unit status reporting

Building integrated circuits using logical units

Hierarchical flush barrier mechanism with deadlock avoidance

Multi-thread FIFO memory generator

Method and apparatus for providing an integrated network of processors

Method and system for reordering isochronous hub streams

Method and apparatus for providing an integrated virtual disk subsystem

Determining memory flush states for selective heterogeneous memory flushes

Accelerated processing via a physically based rendering engine

Accelerated processing via a physically based rendering engine

Accelerated processing via a physically based rendering engine

Accelerated processing via a physically based rendering engine

Accelerated processing via a physically based rendering engine

Power conservation using gray-coded address sequencing

Sequential access memory with master-slave latch pairs and method of operating

Folded FIFO memory generator

Method and apparatus for providing an integrated network of processors

Method and apparatus for performing network processing functions

Internet protocol (IP) router residing in a processor chipset

Multi-threaded FIFO memory generator with speculative read and write capability

Accelerated processing via a physically based rendering engine

Method and apparatus for providing an integrated network of processors

Method and system for automating unit performance testing in integrated circuit design

ALFIERI ROBERT A

Managing multi-threaded FIFO memory by determining whether issued credit count for dedicated class of threads is less than limit

Method and apparatus for performing network processing functions

Deterministic synchronization for transmitting signals between different clock domains

EDMONDSON JOHN H

Coalescing to avoid read-modify-write during compressed data operations

Coalescing to avoid read-modify-write during compressed data operations

Coalescing to avoid read-modify-write during compressed data operations

DATA GENERAL CORP

Apparatus and method for improved CPU affinity in a multiprocessor system

Multiprocessor cluster membership manager framework

EMC CORP

Operating system for a non-uniform memory access multiprocessor system

Method for promotion and demotion between system calls and fast kernel calls

OLIVEIRA MARCIO T

Multi-threaded FIFO memory with speculative read and write capability

RIACH DUNCAN A

Isochronous hub contracts