Inventor

NEZNANOV ILYA V

RU23 patents

⚠️ This page may combine multiple inventors who share the name “NEZNANOV ILYA V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NEZNANOV ILYA V

LSI CORP

Method and apparatus for tiling memories in integrated circuit layout

Method and apparatus for mapping design memories to integrated circuit layout

Method and apparatus for mapping design memories to integrated circuit layout

Soft reed-solomon decoder based on error-and-erasure reed-solomon decoder

Optimization of data processors with irregular patterns

PANTELEEV PAVEL A

Scheme for erasure locator polynomial calculation in error-and-erasure decoder

Variable parity encoder

Reconfigurable encoding per multiple communications standards

Branch metrics calculation for multiple communications standards

Reconfigurable BCH decoder

SOKOLOV ANDREY P

Parallel decoder for multiple wireless standards

Programmable circuit for high speed computation of the interleaver tables for multiple wireless standards

L-value generation in a decoder

SHUTKIN YURII S

Two-pass linear complexity task scheduler

No-delay microsequencer

GASANOV ELYAR E

Timer manager architecture based on binary heap

Radix-4 viterbi forward error correction decoding

LSI LOGIC CORP

RRAM controller built in self test memory

Memory generation and placement

NEZNANOV ILYA V

BCH or reed-solomon decoder with syndrome modification

ANDREEV ALEXANDER

Configurable Reed-Solomon decoder based on modified Forney syndromes

LSICorporation

Low area architecture in BCH decoder

ALISEYCHIK PAVEL A

Parallel true random number generator architecture