Inventor

MATHEWS VIJU K

US40 patents

⚠️ This page may combine multiple inventors who share the name “MATHEWS VIJU K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MATHEWS VIJU K

MICRON TECHNOLOGY INC

Method of forming a capacitor in semiconductor wafer processing

Method for forming a storage cell capacitor compatible with high dielectric constant materials

Advanced technique to improve the bonding arrangement on silicon surfaces to promote uniform nitridation

Method of making semiconductor devices having two-layer gate structure

Method of reducing stress-induced defects in silicon

Process for doping hemispherical grain silicon

Modified LOCOS process for sub-half-micron technology

Low-stress method of fabricating field-effect transistors having silicon nitride spacers on gate electrode edges

Semiconductor processing method of forming an electrically conductive contact plug

Method of forming a field effect transistor

Semiconductor processing method of forming an electrically conductive contact plug

Integrated circuit fabrication process to reduce critical dimension loss during etching

Method of improving resist adhesion for use in patterning conductive layers

Method for forming a storage cell capacitor compatible with high dielectric constant materials

Method for forming a storage cell capacitor compatible with high dielectric constant materials

Method for forming a storage cell capacitor compatible with high dielectric constant materials

Process to improve the flow of oxide during field oxidation by fluorine doping

Methods of forming field oxide and active area regions on a semiconductive substrate

Semiconductor processing method of forming an electrically conductive contact plug

Methods of forming field oxide and active area regions on a semiconductive substrate

Process to improve the flow of oxide during field oxidation by fluorine doping

High pressure nitridation of tungsten

Streamlined field isolation process

Interconnect structure having improved resist adhesion

Semiconductor processing method of forming an electrically conductive contact plug

Methods of forming field oxide and active area regions on a semiconductive substrate

Methods of forming field oxide and active area regions on a semiconductive substrate

Process for stress reduction in silicon during field isolation

Method of forming a field effect transistor

Methods of forming field oxide and active area regions on a semiconductive substrate

Locus isolation technique using high pressure oxidation (hipox) and protective spacers

Method for forming a storage cell capacitor compatible with high dielectric constant materials

Method for forming a storage cell capacitor compatible with high dielectric constant materials

Storage cell capacitor compatible with high dielectric constant materials

Semiconductor wafer isolation structure formed by field oxidation

Semiconductor wafer isolation structure formed by field oxidation

Methods of forming field oxide and active area regions on a semiconductor substrate

MICRON SEMICONDUCTOR INC

Barrier process for Ta2 O5 capacitor

Single mask process for forming both n-type and p-type gates in a polycrystalline silicon layer during the formation of a semiconductor device

Advanced process for recessed poly buffered locos