Inventor

CHIU YI-HSUN

TW87 patents

⚠️ This page may combine multiple inventors who share the name “CHIU YI-HSUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHIU YI-HSUN

TAIWAN SEMICONDUCTOR MFG CO LTD

Memory devices and methods of manufacturing thereof

Integrated circuit structure with backside via rail

Self-aligned etch in semiconductor devices

Low resistance pickup cells for SRAM

Transistors with varying width nanosheet

Memory devices and methods of manufacturing thereof

Fin field effect transistor device structure and method for forming the same

Semiconductor device with reduced leakage current

Vertical device architecture

Semiconductor devices with backside routing and method of forming same

Self-aligned etch in semiconductor devices

Memory devices and methods of manufacturing thereof

Self-aligned etch in semiconductor devices

Semiconductor device including a layer between a source/drain region and a substrate

Methods of forming contact features in field-effect transistors

Gate cut structure and method of forming the same

Fin field effect transistor device structure

Semiconductor device with contact structures

Methods of forming contact features in field-effect transistors

Integrated circuit device including a power supply line and method of forming the same

Semiconductor structures having a micro-battery and methods for making the same

Vertical semiconductor device structure and method of forming

Vertical device architecture

Method of forming masks

Masks based on gate pad layout patterns of standard cell having different gate pad pitches

Backside signal interconnection

Method and apparatus for a seal ring structure

Methods for wafer bonding

CVD apparatus with multi-zone thickness control

Transistors with varying width nanosheet

Semiconductor device including recessed interconnect structure

Integrated circuit structure with backside via rail

Semiconductor transistor devices having double-sided interconnect structures

Dual-side power rail design and method of making same

FinFET SRAM cells with reduced fin pitch

Semiconductor device and method of manufacturing the same

Semiconductor device with contact structures

Methods of forming contact features in field-effect transistors

Separated read BL scheme in 3T dram for read speed improvement

Semiconductor device with L-shape conductive feature and methods of forming the same

Backside power rail for physical failure analysis (PFA)

Semiconductor device including a dielectric layer between a source/drain region and a substrate

Memory devices and methods of manufacturing thereof

Memory devices and methods of manufacturing thereof

Integrated circuit device including a power supply line and method of forming the same

Method for forming fin field effect transistor device structure

Semiconductor device with gate cut structure and method of forming the same

Semiconductor device including recessed interconnect structure

CHIEN TING-YING

Micro electro mechanical system structures

TAIWAN SEMICONDUCTOR MFG

Top metal pads as local interconnectors of vertical transistors