Inventor

IYENGAR VIKRAM

US24 patents

⚠️ This page may combine multiple inventors who share the name “IYENGAR VIKRAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IYENGAR VIKRAM

IBM

Systems and methods for single cell product path delay analysis

IC chip at-functional-speed testing with process coverage evaluation

Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and method

System and method for generating at-speed structural tests to improve process and environmental parameter space coverage

Apparatus and method for selectively implementing launch off scan capability in at speed testing

Design structure for shutting off data capture across asynchronous clock domains during at-speed testing

Method and apparatus for shutting off data capture across asynchronous clock domains during at-speed testing

Efficient scan chain insertion using broadcast scan for reduced bit collisions

Testing of multiple asynchronous logic domains

Systems and methods for single cell product path delay analysis

Method of increasing path coverage in transition test generation

Identifying sequential functional paths for IC testing methods and system

BICKFORD JEANNE P

Test path selection and test program generation for performance testing integrated circuit chips

System yield optimization using the results of integrated circuit chip performance path testing

Integrated circuit product yield optimization using the results of performance path testing

Method and structure for multi-core chip product test and selective voltage binning disposition

Disposition of integrated circuits using performance sort ring oscillator and performance path testing

IYENGAR VIKRAM

Reducing power consumption during manufacturing test of an integrated circuit

Hold transition fault model and test generation method

GILLIS PAMELA S

Method to test hold path faults using functional clocking

BASSETT ROBERT W

System and method for automatically generating test patterns for at-speed structural test of an integrated circuit device using an incremental approach to reduce test pattern count

GRISE GARY D

Clock edge grouping for at-speed test

DENNEAU MONTY M

Online multiprocessor system reliability defect testing

BAALAJI KONDA R

Automatic generation of valid at-speed structural test (ASST) test groups