Inventor

LACKEY DAVID E

US43 patents

⚠️ This page may combine multiple inventors who share the name “LACKEY DAVID E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LACKEY DAVID E

IBM

Voltage island chip implementation

Voltage island chip implementation

Voltage island design planning

Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox

Concurrent logical and physical construction of voltage islands for mixed supply voltage designs

Double-edge-triggered flip-flop providing two data transitions per clock cycle

Latch clustering for power optimization

IC chip at-functional-speed testing with process coverage evaluation

On-board clock-control templates for testing integrated circuits

Integrated circuit device with improved clock signal control

Logic simulation using a hardware accelerator together with an automated error event isolation and trace facility

Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and method

System and method for generating at-speed structural tests to improve process and environmental parameter space coverage

Method of automatic latch insertion for testing application specific integrated circuits

Pipeline array

Microcontroller for logic built-in self test (LBIST)

Nested voltage island architecture

Method for insertion of test points into integrated logic circuit designs

Apparatus and method for selectively implementing launch off scan capability in at speed testing

Latch and clock structures for enabling race-reduced MUX scan and LSSD co-compatibility

Latch and clock structures for enabling race-reduced mux scan and LSSD co-compatibility

Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer

Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer

Negative edge flip-flops for muxscan and edge clock compatible LSSD

Method for insertion of test points into integrated circuit logic designs

Global voltage buffer for voltage islands

Method for testing integrated logic circuits

Apparatus for assisting backside focused ion beam device modification

Testing of multiple asynchronous logic domains

Avoiding race conditions at clock domain crossings in an edge based scan design

Design structure and apparatus for a robust embedded interface

LACKEY DAVID E

Method and device for selectively adding timing margin in an integrated circuit

Method and device for selectively adding timing margin in an integrated circuit

Method and device for selectively adding timing margin in an integrated circuit

Method and device for selectively adding timing margin in an integrated circuit

BICKFORD JEANNE P

Test path selection and test program generation for performance testing integrated circuit chips

Disposition of integrated circuits using performance sort ring oscillator and performance path testing

GRISE GARY D

Microcontroller for logic built-in self test (LBIST)

Microcontroller for logic built-in self test (LBIST)

WARNOCK JAMES DOUGLAS

LSSD compatibility for GSD unified global clock buffers

GILLIS PAMELA S

Dense register array for enabling scan out observation of both L1 and L2 latches

EUSTIS STEVEN M

Method and apparatus for a robust embedded interface

IYENGAR VIKRAM

Hold transition fault model and test generation method