Inventor

VILLARRUBIA PAUL G

US41 patents

⚠️ This page may combine multiple inventors who share the name “VILLARRUBIA PAUL G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VILLARRUBIA PAUL G

IBM

Clock aware placement

Latch placement for high performance and low power circuits

Analytical constraint generation for cut-based global placement

System and method for sign-off timing closure of a VLSI chip

Timing adjustments across transparent latches to facilitate power reduction

Structured placement of latches/flip-flops to minimize clock power in high-performance designs

Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors

Constrained detailed placement

Boundary latch and logic placement to satisfy timing constraints

Post-placement cell shifting

Method of minimizing early-mode violations causing minimum impact to a chip design

Buffer-aware routing in integrated circuit design

Multi power synthesis in digital circuit design

Large cluster persistence during placement optimization of integrated circuit designs

Routing centric design closure

Integer arithmetic method for wire length minimization in global placement with convolution based density penalty computation

Detailed routability by cell placement

Memory element graph-based placement in integrated circuit design

Structured placement of hierarchical soft blocks during physical synthesis of an integrated circuit

Propagating constants of structured soft blocks while preserving the relative placement structure

Automated design closure with abutted hierarchy

Short net pin alignment for routing

Enhanced alignment for global placement in a circuit

Power staple avoidance for routing via reduction

Enhancing stability of half perimeter wire length (HPWL)-driven analytical placement

Memory element graph-based placement in integrated circuit design

Bit flip aware latch placement

Model-based refinement of the placement process in integrated circuit generation

Facilitating the design of a clock grid in an integrated circuit

Large cluster persistence during placement optimization of integrated circuit designs

Large cluster persistence during placement optimization of integrated circuit designs

Scheduling for parallel processing of regionally-constrained placement problem

Multi-cycle latch tree synthesis

Region-based power grid generation through modification of an initial power grid based on timing analysis

Hierarchy-driven logical and physical synthesis co-optimization

ALPERT CHARLES J

Post-placement cell shifting

Element placement in circuit design based on preferred location

MOFFITT MICHAEL D

Partitioning for hardware-accelerated functional verification

Partitioning for hardware-accelerated functional verification

NAM GI-JOON

Scheduling for parallel processing of regionally-constrained placement problem

Scheduling for parallel processing of regionally-constrained placement problem